• Journal of Communications and Networks
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• v.7 no.3
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• pp.248-257
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• 2005

In this paper, we develop design procedures for carrier tracking loop for orthogonal frequency division multiplexing (OFDM) systems or other systems of blocked data. In such communication systems, phase error measurements are made infrequent enough to invalidate the traditional loop design methodology which is based on analog loop design. We analyze the degradation in the OFDM schemes caused by the tracking loop and show how the performance is dependent on the rms phase error, where we distinguished between the effect of the variance in the average phase over the symbol and the effect of the phase change over the symbol. We derive the optimal tracking loop including optional delay in the loop caused by processing time. Our solution is general and includes arbitrary phase noise apd additive noise spectrums. In order to guarantee a well behaved solution, we have to check the design against margin constraints subject to uncertainties. In case the optimal loop does not meet the required margin constraints subjected to uncertainties, it is shown how to apply a method taken from control theory to find a controller. Alternatively, if we restrict the solution to first or second order loops, we give a simple loop design procedure which may be sufficient in many cases. Extensions of the method are shown for using both pilot symbols and data symbols in the OFDM receiver for phase tracking. We compare our results to other methods commonly used in OFDM receivers and we show that a large improvement can be gained.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.24 no.10A
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• pp.1597-1602
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• 1999

An analog / digital mixed mode frequency multiplication and distribution ASIC for switch link or network synchronization of ATM switching system for B-ISDN has designed. This ASIC generates 234-7 MHz system clock and 77.76 MHz, 19.44 MHz user clocks using 46.94 MHz external clock. It also includes digital circuits for checking and selecting between the two external clocks. For effective ASIC design, full custom technique is used in analog PLL circuit and standard cell based technique is used in digital circuit. Resistors and capacitors are specially designed so the chip can be implemented in 0.8$\mu\textrm{m}$ digital CMOS technology.

• Journal of Power Electronics
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• v.13 no.3
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• pp.487-496
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• 2013

The three-phase synchronous reference frame phase-locked loop (SRF-PLL) is widely used for synchronization applications in power systems. In this paper, a new control strategy for three-phase grid-connected LCL inverters without a PLL is presented. According to the new strategy, a current reference can be generated by using the instantaneous power control scheme and the proposed positive-sequence voltage detector. Through theoretical analysis, it is indicated that a high-quality grid current can be produced by introducing the new control strategy. In addition, a kind of independent control for reactive power can be achieved under unbalanced and distorted grid conditions. Finally, the excellent performance of the proposed control strategy is validated by means of simulation and experimental results.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.64 no.12
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• pp.1709-1717
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• 2015

In remote islands PV (Photo Voltaic) panel with BESS (Battery Energy Storage System) supplies electric power to the customers in parallel operation with EG (Engine Generator) to save fuel consumption and to mitigate environmental load. BESS operates in voltage control mode when it supplies power to the load alone, while it operates in current control mode when it supplies power to the load in parallel with EG. This paper proposes a smooth mode change scheme from current control to voltage control of BESS by adding proper initial value to the integral part of voltage control, and a smooth mode change scheme from voltage control to current control by tracking the EG output voltage to the BESS output voltage using PLL (Phase-Locked Loop). The feasibility of proposed schemes was verified through computer simulations with PSCAD/EMTDC, and the feasibility of actual hardware system was verified by experiments with scaled prototype. It was confirmed that the proposed schemes offer a seamless operation in the stand-alone power system in remote islands.

• Journal of Power Electronics
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• v.18 no.5
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• pp.1523-1535
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• 2018

High-performance Phase-Locked Loops (PLLs) are critical for grid synchronization in grid-tied power electronic applications. In this paper, a new single-phase All Digital Phase-Locked Loop (ADPLL) is proposed. It features fast transient response and good robustness under distorted grid conditions. It is designed for Field Programmable Gate Array (FPGA) implementation. As a result, a high sampling frequency of 1MHz can be obtained. In addition, a new OSG is adopted to track the power frequency, improve the harmonic rejection and remove the dc offset. Unlike previous methods, it avoids extra feedback loop, which results in an enlarged system bandwidth, enhanced stability and improved dynamic performance. In this case, a new parameter optimization method with consideration of loop delay is employed to achieve a fast dynamic response and guarantee accuracy. The Phase Detector (PD) and Voltage Controlled Oscillator (VCO) are realized by a Coordinate Rotation Digital Computer (CORDIC) algorithm and a Direct Digital Synthesis (DDS) block, respectively. The whole PLL system is finally produced on a FPGA. A theoretical analysis and experiments under various distorted grid conditions, including voltage sag, phase jump, frequency step, harmonics distortion, dc offset and combined disturbances, are also presented to verify the fast dynamic response and good robustness of the ADPLL.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.62 no.2
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• pp.201-207
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• 2013

This paper propose seamless transfer operation between grid-connected and stand-alone mode in the three-phase inverter for microgrid. The inverter operates grid-connected mode and stand-alone mode. Grid-connected mode is the inverter connected to grid and stand-alone mode is to deliver energy to the load from inverter at grid fault. When conversion from gird-connected to stand-alone mode, the inverter changes current control to voltage control. When grid restored, the inverter system is conversion from stand-alone to grid-connected mode. In this case, load phase and grid phase are different. Therefore, synchronization is essential. Thus Seamless transfer operation stand-alone to grid-connected mode. In this paper, propose sealmless transfer operation between grid-connceted and stand-alome mode, and this method is verified through simulation and experiment.

• Proceedings of the Korean Information Science Society Conference
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• 1998.10a
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• pp.68-70
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• 1998

본 논문에서는 클록들을 주기적으로 동기화하는 분산 실시간 시스템에서 주어진 태스크의 시간 제약(timing constraint)을 변환시는 구가지 기법을 제안한다. 전형적인 이산 클록 동기화(discrete clock synchronization)알고리즘은 클록의 값을 순간적으로 보정(correct)하여 클록의 시간이 불연속적으로 진행학 한다. 이러한 시간상의 불연속성은 태스크의 시작제한시간(release time)이나 종료시한(deadline)과 같은 이벤트를 잃어버리거나 다시 발생시키는 오류를 범하게 한다. 클록 시간의 불연속성을 피하기 위해 일반적으로 연속 클록 동기화(continuous clock synchronization) 기법이제안되었지만 소프트웨어적으로 구현되기에는 많은 오버헤드를 유발시키는 문제점이 있다. 이에 따라 연속 클록 동기화는 PLL (Phase-Locked Loop)을 이용한 별도의 하드웨어를 사용하는 것이 보통이다. 본 논문에서는 연속 클록 동기화 기법을 사용하는 대신, 태스크의 시간 제약을 동적으로 변환시키는 DCT (Dynamic Constraint Transformation) 기법을 제안하였다. DCT는 소프트웨어 으로 구현이 가능하여 새로운 하드웨어를 필요로 하지 않으며, 이를 통해 기존의 이산적으로 동기화된 시스템에서 클록 시간의 불연속성에 의한 문제점들을 해결할 수 있다. 또 다른 문제점으로서, 클록의 물리적인 특성으로 인해 동기화된 클록들이 상한된(bounded from the above)오차(skew)를 갖는다는 것이다. 이러한 오차는 지역 클록(local clock)에 대해 만족될 수 있는 임의의 실기간 제약 조건이 전역 클록(global clock)에 대해서는 만족되지 않을 수 있음을 의미한다. 본 논문에서는 이를 위해 먼저 두 가지의 스케줄링 가능성, 지역적 스케줄링 가능서(local schedulability)과 전역적 스케줄링 가능성(global schedulability)을 정의하고, 실시간 제약을 정적으로 변환시키는 SCT (Static Constraint Transformation)기법을 제안하였다. SCT를 통해 지역적으로 스케줄링 가능한 태스크는 전역적으로 스케줄링이 가능하므로, 단지 지역적 스케줄링 가능성만을 검사하면서 스케줄링 문제를 해결할 수 있도록 하였다.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.15 no.10 s.89
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• pp.952-960
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• 2004

PSK(Phase Shift Keying) is useful because of the power and spectral efficient modulation. In this paper, no additional hardware will be needed to support various transmit mode in the suggested DSP scheme. We design and implement the synchronization algorithm for M-ary PSK(M=2, 4) demodulator based on DSP scheme, instead of complex analog PSK demodulator. TMS320C6203 is used as DSP. We check the all kinds of waveforms via the graph view window after software programming the emulation on the DSP tool. The result of implementation proves that demodulator using the suggested algorithm has equal performance with demodulator using analog circuits.

• Proceedings of the IEEK Conference
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• 2000.09a
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• pp.55-58
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• 2000

본 논문에서는 제한된 통신 채널의 대역에서 주파수 효율이 높은 OFDM 시스템을 위한 반송파 주파수 동기 알고리즘을 제안한다. OFDM 시스템에서의 반송파 주파수 옵셋은 부반송파 간격의 정수배와 소수배로 나누어진다 소수배 주파수 옵셋이 ± 0.5 근처의 값을 가질 경우에는 정확한 정수배 주파수 옵셋 추정이 어렵고 반송파 동기 PLL이 소수배 주파수 옵셋을 추적하는데 많은 시간이 소요된다. 제안한 알고리즘은 정수배 주파수 옵셋을 제거하기 위해 2개의 심볼 만을 이용하고 다중경로 패널에서도 정확한 정수배 주파수 옵셋의 추정이 가능하다 또한, 소수배 주파수 옵셋이 ± 0.5 근처의 값을 가질 경우 적은 계산량으로 주파수 옵셋을 ± 0.1 이내로 보상할 수 있다.

• The Transactions of the Korean Institute of Power Electronics
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• v.20 no.2
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• pp.152-159
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• 2015

In a weak grid condition, the precise grid impedance estimation is essential to guaranteeing the high performance current control and power transfer for a grid-connected inverter. This study proposes a precise estimation method for grid impedance by PQ variations by employing the variation method of reference currents. The operation principle of grid impedance estimation is fully presented, and the negative impact of the phase locked loop is analyzed. Estimation error by a synchronization angle in the park's transformation using the phase locked loop is derived. As a result, the variation method of reference currents for accurate estimation is introduced. The validation of the proposed method is verified through several simulation results and experiments based on a 2-kW voltage source inverter prototype.