• Journal of the Institute of Electronics Engineers of Korea CI
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• v.45 no.6
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• pp.87-93
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• 2008

This paper describes implementation of the 5.0GHz RF frequency synthesizer with $0.18{\mu}m$ silicon CMOS technology being used as an application of the IEEE802.15.4 USN sensor node transceiver modules. To get good performance of speed and noise, design of the each module like VCO, prescaler, 1/N divider, fractional divider with ${\Sigma}-{\Delta}$ modulator, and common circuits of the PLL has been optimized. Especially to get good performance of speed, power consumption, and wide tuning range, N-P MOS core structure has been used in design of the VCO. The chip area including pads for testing is $1.1*0.7mm^2$, and the chip area only core for IP in SoC is $1.0*0.4mm^2$. Through comparing and analysing of the designed two kind of the frequency synthesizer, we can conclude that if we improve a litter characteristics there is no problem to use their as IPs.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.17 no.10
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• pp.2409-2418
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• 2013

Two frequency synthesizers are proposed to generate a clock for a sub-sampler of an on-chip oscilloscope in this paper. These proposed frequency synthesizers are designed by using a multi-phase delayed-locked loop (DLL)-based phase selector and a fractional-N phase-locked loop (PLL), and they are analyzed by comparing simulation results of each frequency synthesizer. Two proposed frequency synthesizers are designed using a 65-nm CMOS process with a 1V supply and output the clock with the frequency of 121.15 MHz when the frequency of an input clock is 125 MHz. The designed frequency synthesizer using a multi-phase DLL-based phase selector has the area of 0.167 $mm^2$ and the peak-to-peak jitter performance of 2.88 ps when it consumes the power of 4.75 mW. The designed frequency synthesizer using a fractional-N PLL has the area of 0.662 $mm^2$ and the peak-to-peak jitter performance of 7.2 ps when it consumes the power of 1.16 mW.

• IEIE Transactions on Smart Processing and Computing
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• v.4 no.3
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• pp.141-144
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• 2015

A broadband radio frequency synthesizer for multi-band, multi-standard mobile DTV tuners is proposed, it's loop bandwidth can be calibrated to optimize integrated phase noise performance without the problem of phase noise peaking. For this purpose, we proposed a new third-order scalable loop filter and a scalable charge pump circuit to minimize the variation in phase margin during calibration. The prototype phase-lock loop is fabricated in 180nm complementary metal-oxide semiconductor shows that it effectively prevents phase noise peaking from growing while the loop bandwidth increases by up to three times.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.49 no.1
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• pp.85-91
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• 2012

In this paper, we implemented a Ka-band frequency synthesizer for millimeter wave seeker. we designed for high frequency resolution and frequency hopping response time in the digital synthesis method which uses DDS(Direct Digital Synthesizer). but frequency bandwidth was limited low frequency because DDS output frequency was limited 1/2 by system clock. thus, frequency synthesizer was converted to Ka-band using the frequency multiplier ${\times}4$ and local oscillator. proposed frequency synthesizer was bandwidth 500MHz, frequency switching time was $0.7{\mu}s$, spurious level was suppressed below -52dBc. phase noise was -99dBc/Hz at offset 100kHz and flatness was ${\pm}1dB$.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.22 no.11
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• pp.1117-1124
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• 2011

In this paper, we implemented a Ka-band frequency synthesizer for millimeter wave seeker. We improved frequency synthesizer performance of phase noise, resolution and spurious using the DDS driven hybrid method The proposed frequency synthesizer has the bandwidth of 1 GHz, frequency switching time of below 9 ${\mu}s$, suppressed spurious level of below -68.9 dBc. phase noise of -113.58 dBc/Hz at offset 100 kHz and flatness of ${\pm}$0.7 dB.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.23 no.11
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• pp.1280-1287
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• 2012

The 3.2~6.5 GHz wideband YTO(YIG Tuned Oscillator) module is designed, fabricated and measured. To improve the phase noise characteristic of the YTO module, offset PLL(Phase Locked Loop) structure with sampling mixer is applied. This YTO module is composed of sampling mixer, phase detector, loop filter, current driver, and YTO. The phase noise of the fabricated YTO module is measured as -100 dBc/Hz at 10 kHz offset frequency, which approximates the predicted result at the center frequency of 4.5 GHz. This YTO module presents over 10 dB improved phase noise compared to conventional PLL module from operating frequency.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.16 no.10
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• pp.914-924
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• 1991

It has been generally used for PLL(Phase Locked Loop) to be synthesized randomly chosen frequency state, but the PLL locking time was inevitable element. A direct digital synthesizer. Which makes output frequency directly in sine wave by a phase accumulating method, could be leiminate the defect, although a phase distortion in frequency spectrum. In order to improve this disadvantage, the phase accumulating method is reconsidered in the side of he output wave formula expression. A new mechanism is proposed, and it is constructed by a most suitable logic elements. The spectrum of synthesized sine waveform is simulated and compared with a measured value, and it’s the coherence frequency hoppong state with the PN(Pseudo Noise) code sequence is confirmed. In this results, the power levels of phase distortion harmonics are decreased to 10~25dB and bandwidths are increased to 420kHz.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 1998.05a
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• pp.258-264
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• 1998

본문에서 주파수hopping과 이동통신에서 요구되는 고속 주파수 전환이 가능한 새로운 주파수 신시사이저 (Synthesizer)를 제안한다. 종래의 PLL 주파수 신시사이저는 기준 주파수와 출력의 채널 주파수 간격이 동일하기 때문에 기준 주파수를 낮게 하면 매우 긴 동기 시간이 소요된다. 본 논문에서 제안하는 주파수 신시사이저는 새로운 제어 방법을 이용한 다단 펄스 제거 회로를 사용하여 기준 주파수와 채널 간격 주파수를 독립적으로 설정할 수 있기 때문에 종래의 신시사이저와 동일한 채널 간격의 주파수를 유지시키면서 기준 주파수를 높일 수 있고, 또한 루프(loop)이득을 크게 할 수 있다. 따라서 종래의 주파수 신시사이저보다 주파수 절환시간을 크게 단축할 수 있다. 본 논문에서는 주파수 절환시간을 1/100 정도 단축시킬 수 있음을 보여주고 있다.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.15 no.2
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• pp.152-158
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• 2004

A low phase noise frequency synthesizer at X-Band which employs the subharmonic injection locking was designed and tested. The designed frequency synthesizer consists of a 1.75 GHz master oscillator - which also operates as a harmonic generator - and a 10.5 GHz slave oscillator. A 1.75 GHz master oscillator based on PLL technique used two transistors - one constitutes the active part of VCO and the other operates as a buffer amplifier as well as harmonic generator. The first stage operates a fixed locked oscillator and using the BJT transistor whose cutoff frequency is 45 GHz, the second stage is designed, operating as a harmonic generator. The 6th harmonic which is produced from the harmonic generator is injected into the following slave oscillator which also behaves as an amplifier having about 45 dB gain. The realized frequency synthesizer has a 7.4 V/49 mA, -0.5 V/4 mA of the low DC power consumption, 4.53 dBm of output power, and a phase noise of -95.09 dBc/Hz and -108.90 dBc/Hz at the 10 kHz and 100 kHz offset frequency, respectively.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.14 no.8
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• pp.777-786
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• 2003

The phase noise characteristics of the phase-locked loop frequency synthesizer were predicted based on the analysis for phase noise contribution of noise sources. The proposed phase noise model in this paper more accurately predicts the phase noise spectrum of frequency synthesizer. To accurately model the phase noise contribution of noise sources in frequency synthesizer, the phase noise sources were analyzed via modeling of the frequency divider and phase noise components using Leeson model for reference signal source and VCO. The phase noise transfer functions to VCO from noise sources were analyzed by superposition theory and linear operation of phase-locked loop. To evaluate the phase noise prediction model, the frequency synthesizers were fabricated and were evaluated by measured data and prediction data.