• Proceedings of the IEEK Conference
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• 2003.11c
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• pp.37-40
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• 2003

The 1.63㎓, 2.33㎓ dual-band PLL frequency synthesizer has been developed for applications to the miniature repeater. The miniature dual-band repeater will be used at shopping mall, basements and underground parking lots. The in-loop 1.63㎓, 2.33㎓ dual-band PLL frequency synthesizer has been developed by designing Si BJT VCO and PLL loop circuits with Colpitts. The prototype of 1.63㎓, 2.33㎓ dual-band PLL frequency synthesizer of size 19${\times}$19${\times}$8(mm) has shown operating frequencies of 1.63㎓, 2.33㎓ ranges, RF output of 1dBm(PCS), 1dBm(IMT-2000), phase noise of -100 dBc/Hz(PCS), -95dBc/Hz(IMT-2000) at 10KHz offset, harmonics suppression of -24dB c(PCS), -15dBc(IMT-2000).

• Journal of Power Electronics
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• v.11 no.5
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• pp.632-638
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• 2011

This paper presents a cascaded coil flux control based on a Current Source Parallel Resonant Push-Pull Inverter (CSPRPI) for Induction Heating (IH) applications. The most important problems associated with current source parallel resonant inverters are start-up problems and the variable response of IH systems under load variations. This paper proposes a simple cascaded control method to increase an IH system's robustness to load variations. The proposed IH has been analyzed in both the steady state and the transient state. Based on this method, the resonant frequency is tracked using Phase Locked Loop (PLL) circuits using a Multiplier Phase Detector (MPD) to achieve ZVS under the transient condition. A laboratory prototype was built with an operating frequency of 57-59 kHz and a rated power of 300 W. Simulation and experimental results verify the validity of the proposed power control method and the PLL dynamics.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2005.06a
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• pp.284-288
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• 2005

This paper proposes the direct detection method of phase angle for the power source, which is based on the PLL method. The proposed method using a bidirectional photo-coupler is used to directly detect the zero crossing of phase voltage and calculate the angular frequency in the controller based on a M/T algorithm. Through the method, the additional installation space in the traditional method using a potential transformer can be minimized and it can be easy to design. The paper presents straightforward schematic circuits, design and experimental results.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2003.10a
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• pp.394-397
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• 2003

Since the speed of operation in the system has been increasing rapidly, chips should have been synchronized. Then, synchronized circuits such as PLL (Phase Locked Loop), DLL (Delay Locked Loop) are used. VCO (Voltage Controled Oscillator) generated a frequency in the PLL has disadvantage such as jitter accumulation. On the other hands, VCDL (Voltage Controled Delay Line) used at DLL has an advantage which has no jitter accumulation. In this paper, a new and improved VCDL structure is suggested.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.16 no.4
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• pp.301-308
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• 1991

In this paper, we have proposed a demodulation circuit of radio data receiver system and calculated the error probability of the digital transmitted signal corrupted under noise environment. And we have evaluated the error performance of the proposed system. The designed demodulation circuits have been implemented by using the general random logic and PLL circuits, which can be possible for the integrated circuit design of the radio data receiver system. In addition calculation of bit error rate in recovered digital signal has been accomplished ans we have confirmed that the proposed system hsa the equivalent performance with already existing ones.

• JSTS:Journal of Semiconductor Technology and Science
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• v.7 no.1
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• pp.11-19
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• 2007

This paper presents two novel compensation circuits for leakage current and power supply noise (PSN) in phase locked loop (PLL) using a nanometer CMOS technology. The leakage compensation circuit reduces the leakage current of the charge pump circuit which becomes more serious problem due to the thin gate oxide and small threshold voltage in nanometer CMOS technology and the PSN compensation circuit decreases the effect of power supply variation on the output frequency of VCO. The PLL design is based on a 32nm predictive CMOS technology and uses a 0.9V power supply voltage. The simulation results show that the proposed PLL achieves a 88% jitter reduction at 440MHz output frequency compared to the PLL without leakage compensator and its output frequency drift is little to 20% power supply voltage variations. The PLL has an output frequency range of $40M{\sim}725MHz$ with a multiplication range of 11023, and the RMS and peak-to-peak jitter are 5ps and 42.7ps, respectively.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.19 no.9
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• pp.1692-1701
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• 1994

Macromodeling technology is useful to simulate and analyze the performance of new elements and complicated circuits or systems without any changes in today's general simulator, PSPICE. In this paper, Phase Locked Loop(PLL) is designed using macromodeling technique. The PLL macromodel has two basic sub-macromodels of the phase detector and the voltage controlled oscillator(VCO). The PLL macromodel has two open terminals for inserting RC low pass filter. The PLL macromodel is simulated using simulation parameters of LM565CN manufactured in the National company. At a free-running frequency, 2500Hz, upper lock range and lower capture range was 437Hz, 563Hz, respectively. Also, experimental results and simulation results of LM565CN PLL show good agreement.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.20 no.12
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• pp.1325-1332
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• 2009

In this paper, we design a 2.4 GHz bio-radar system that can detect human heartbeat and respiration signals with small size and improved noise performance using single circular-polarized antenna and phase-locked loop. The demonstrated bio-radar system consists of single circular-polarized antenna with $90^{\circ}$ hybrid, low-noise amplifier, power amplifier, voltage-controlled oscillator with phase-locked loop circuits, quadrature demodulator and analog circuits. To realize compact size, the printed annular ring stacked microstrip antenna is integrated on the transceiver circuits, so its dimension is just $40\times40mm^2$. Also, to improve signal-to-noise-ratio performance by phase noise due to transmitter leakage signal, the phase-locked loop circuit is used. The measured results show that the heart rate and respiration accuracy was found to be very high for the distance of 50 cm without the additional digital signal processing.

• Journal of IKEEE
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• v.7 no.2 s.13
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• pp.236-244
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• 2003

In this paper, RF and IF circuits for mobile terminals which have usually been implemented using expensive BiCMOS processes are designed using CMOS circuits, and a Tx CMOS RF/IF single chip for PCS applications is designed. The designed circuit consists of an IF block including an IF PLL frequency synthesizer, an IF mixer, and a VGA and an RF block including a SSB RF mixer and a driver amplifier, and performs all transmit signal processing functions required between digital baseband and the power amplifier. The phase noise level of the designed IF PLL frequency synthesizer is -114dBc/Hz@100kHz and the lock time is less than $300{\mu}s$. It consumes 5.3mA from a 3V power supply. The conversion gain and OIP3 of the IF mixer block are 3.6dB and -11.3dBm. It consumes 5.3mA. The 3dB frequencies of the VGA are greater than 250MHz for all gain settings. The designed VGA consumes 10mA. The designed RF block exhibits a gain of 14.93dB and an OIP3 of 6.97dBm. The image and carrier suppressions are 35dBc and 31dBc, respectively. It consumes 63.4mA. The designed circuits are under fabrication using a $0.35{\mu}m$ CMOS process. The designed entire chip consumes 84mA from a 3V supply, and its area is $1.6㎜{\times}3.5㎜$.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.28 no.7
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• pp.540-549
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• 2017

A phase frequency detector(PFD) composed of logic circuits is widely used in a phase locked loop(PLL) due to the easy implementation for integrated circuits. A frequency locked loop(FLL) removes the reference oscillator in the PLL, and the resonator serves as a reference oscillator. A frequency detector(FD) is indispensable for the FLL configuration, and a FD, which is usually composed of a mixer is used to build an FLL. In this paper, instead of FD using mixer, a FD is constructed by using 1.175 GHz resonator composed of microstrip and PFD taking the versatility of PFD into consideration. Using the designed FD, FLL oscillating at a frequency of 1.175 GHz is composed. As a result of comparison with the FLL composed of FD using mixer, it was confirmed that the proposed FLL has better phase noise performance than FLL using mixer FD with FLL bandwidth.