• 전기학회논문지P
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• 제54권3호
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• pp.111-118
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• 2005

Since the residential load is an AC load and the output of solar cell is DC power, the photovoltaic system needs the DC/AC converter to utilize solar cell. In case of driving to interact with utility line, in order to operate at unity power factor, converter must provide the sinusoidal wave current and voltage with same phase of utility line. Since output of solar cell is greatly fluctuated by insolation, it is necessary that the operation of solar cell output in the range of the vicinity of maximum power point. In this paper, DC/AC converter is three phase PWM converter with smoothing reactor. And then, feed-forward control used to obtain a superior characteristic for current control and digital PLL circuit used to detect the phase of utility line.

• 대한전자공학회논문지SD
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• 제45권4호
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• pp.21-26
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• 2008

본 논문에서는 Instantaneous locking 특성을 갖는 새로운 구조의 수동형 광가입자망용 622Mbps급 버스트모드 클럭/데이터 복원회로를 제안하고, 이를 구현하였다. 이 회로는 고속 클럭신호를 발생하는 위상고정루프 와 버스트모드에서의 클럭/데이터 복원회로 두 개의 블럭으로 구성되어 있다. 클럭/데이터 복원회로 에서는 위상고정루프의 클럭을 지연소자를 통해 7개의 서로 다른 클럭신호로 발생시킨다. 이 경우 광가입자망에 지터를 가지고 있는 신호가 입력되어도 항상 데이터의 중앙에 클럭이 정렬되도록 조정하여 최적의 샘플링 시점에서 데이터를 복원하게 된다. 제안한 구조에 대한 검증을 위하여 0.35umn-well CMOS 공정을 이용하여 회로의 동작을 확인하였다.

• 조명전기설비학회논문지
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• 제19권6호
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• pp.100-108
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• 2005

본 논문은 제주-해남 HVDC 시스템의 주파수 제어를 다루었다. 논문의 주된 목적은 현재 사용되고 있는 동기조상기로부터의 주파수 입력원을 배제한 새로운 주파수 제어시스템을 개발하여 대체를 검증하는 것이다. 과도상태의 검토는 PSCAD/EMTDC를 이용하여 상세 모델링으로 구현하였으며, 개발된 HVDC 모델을 통하여 동기조상기의 운전정지와 계통변화에 대한 사고를 검토하였다. 결론적으로 본 논문에서는 모의실험을 통하여 현재의 동기조상기로부터 HVDC 주파수 신호원을 검출하는 것에 비하여 새로운 주파수 제어 알고리즘을 적용한 154[kV] 모선으로 변경이 제주 AC 계통의 변화에 좀더 능동적으로 대처할 수 있음을 확인하였다.

• 한국정보통신학회논문지
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• 제15권7호
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• pp.1552-1558
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• 2011

본 논문에서는 전압제어지연단(Voltage Controlled Delay Line : VCDL)을 이용하여 기존의 위상고정루프와 다른 형태의 위상 지연고정루프(Phase Delay Locked Loop)를 제안하였다. 이 구조를 이용하여 기존의 위상고정루프의 2차 또는 3차 루프필터(Loop Filter)를 단하나의 커패시터로 구현하여 칩의 크기를 크게 줄였다. 새로이 제안하는 듀얼루프 위상 자연고정루프에서는 전압제어지연단 경로의 커패시터와 전하펌프의 전류 크기를 조절함으로서 작은 이득 값을 가지는 전압제어지연단을 사용할 수 있다. 제안된 회로는 $0.18{\mu}m$ CMOS 공정의 파라미터를 이용하여 Hspice로 시뮬레이션을 수행하고 회로의 동작을 검증하였다.

• Journal of Power Electronics
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• 제18권5호
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• pp.1523-1535
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• 2018

High-performance Phase-Locked Loops (PLLs) are critical for grid synchronization in grid-tied power electronic applications. In this paper, a new single-phase All Digital Phase-Locked Loop (ADPLL) is proposed. It features fast transient response and good robustness under distorted grid conditions. It is designed for Field Programmable Gate Array (FPGA) implementation. As a result, a high sampling frequency of 1MHz can be obtained. In addition, a new OSG is adopted to track the power frequency, improve the harmonic rejection and remove the dc offset. Unlike previous methods, it avoids extra feedback loop, which results in an enlarged system bandwidth, enhanced stability and improved dynamic performance. In this case, a new parameter optimization method with consideration of loop delay is employed to achieve a fast dynamic response and guarantee accuracy. The Phase Detector (PD) and Voltage Controlled Oscillator (VCO) are realized by a Coordinate Rotation Digital Computer (CORDIC) algorithm and a Direct Digital Synthesis (DDS) block, respectively. The whole PLL system is finally produced on a FPGA. A theoretical analysis and experiments under various distorted grid conditions, including voltage sag, phase jump, frequency step, harmonics distortion, dc offset and combined disturbances, are also presented to verify the fast dynamic response and good robustness of the ADPLL.

• 전기학회논문지P
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• 제59권2호
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• pp.135-140
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• 2010

This paper presents a sensorless speed control of BLDC Motor using terminal voltage of the one phase. Rotor position information is extracted by indirectly sensing the back EMF from only one of the three terminal voltages for a three-phase BLDC motor. Depending on the terminal voltage sensing rotor position, active filter is used for position information. This leads to a significant reduction in the component device of the sensorless circuit. Therefore this is a advantage for the cost saving and size reduction. With indirect sensing methods based on detection of the terminal voltage that require active filtering, the position information needs the six divider section by PLL circuit, the binary counter and johnson counter by the EPLD. Finally, this algorithm can estimate the rotor position information similar to Hall-sensor sticked the three-phase BLDC motor. As a result, the method described that it is not sensitive to filtering delays, allowing the motor to achieve a good performance over a wide speed range. In addition, a simple starting method and a speed estimation approach are also proposed. Experimental and simulation results are included to verify the proposed scheme.

• The Korean Journal of Physiology and Pharmacology
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• 제8권6호
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• pp.329-333
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• 2004

In this study, we investigated whether TNF-alpha, IL-1beta, CTMA (carboxymethyl trimethylammonium) and LPD (Lup-20[29]-ene-3beta,28-diol) affect mucin release from airway goblet cells and compared the activities of these agents with the inhibitory action of PLL and the stimulatory action of ATP on mucin release. Confluent primary hamster tracheal surface epithelial (HTSE) cells were metabolically radiolabeled with $^3H-glucosamine$ for 24 h and chased for 30 min in the presence of varying concentrations of each agent to assess the effects on $^3H-mucin$ release. The results were as follows: TNF-alpha, CTMA and LPD increased mucin release at the highest concentration, but IL-1beta did not. We conclude that CTMA and LPD can stimulate mucin release by directly acting on airway mucin-secreting cells, and suggest that these agents should be further investigated for the possible use as mild expectorants during the treatment of chronic airway diseases.

• 전력전자학회논문지
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• 제10권5호
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• pp.457-467
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• 2005

본 논문은 해남에서 제주로 연결되어 운전중인 HVDC 시스템의 새로운 주파수 제어기에 대하여 연구하였다. 연구의 첫 번째 목적은 현재의 동기조상기를 제거하기 위하여 새로운 주파수 제어기를 개발하고, 평가를 수행하는 것이다. 모의실험 케이스를 만들기 위하여 PSCAD/EMTDC와 PSS/E를 혼합하여 사용하였고 주 시스템 연구는 과도상태 분석을 위하여 PSCAD/EMTDC을 사용하였다. 연구 케이스는 3상과 1상 지락 그리고 부하탈락에 대한 사고를 모의하였고 연구결과를 나타내었다. 결론적으로 AC 네트워크로부터 검출되는 새로운 주파수 측정 방법은 유효한 주파수 제어와 동적 성능을 나타냄을 알 수 있었다.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2004년도 전력전자학술대회 논문집(1)
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• pp.133-136
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• 2004

Since the residential load is an AC load and the output of solar cell is a DC power, the photovoltaic system needs the DC/AC converter to utilize solar cell. In case of driving to interact with utility line, in order to operate at unity power factor, converter must provide the sinusoidal wave current and voltage with same phase of utility line. Since output of solar cell is greatly fluctuated by insolation, it is necessary that the operation of solar cell output in the range of the vicinity of maximum power point. In this paper, DC/AC converter is three phase PWM converter with smoothing reactor. And then, feedforward control used to obtain a superior characteristic for current control and digital PLL circuit used to detect the phase of utility line.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2006년 학술대회 논문집 정보 및 제어부문
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• pp.394-396
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• 2006

When developing a new GPS receiver module, the essential problems are evaluation of reliable algorithms, software debugging, and performance comparison between algorithms to find optimal solution. Most GPS receiver modules nowadays use a correlator to track signals from satellites and an MCU (Micro Controller Unit) to control operations of the entire module. The problem of software evaluation from MCU is very difficult, due to limitation of MCU resources and low ability of interfacing with user. Normally, user has to expense special tool kit for a limiting access to MCU but it is also hard to use. This article introduces an implementation of a GPS receiver test bed using correlator GP2021 interfacing with ISA (Industry Standard Architecture) PC bus. This way can give user complete control and visibility into the operation of the receiver, then user can easily debug program and test algorithms. For this article, the least square method is implemented to test the hardware and software performance.