• 한국전자파학회:학술대회논문집
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• 한국전자파학회 2000년도 종합학술발표회 논문집 Vol.10 No.1
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• pp.206-210
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• 2000

본 논문에서는 PLL 주파수 합성기를 이용한 900 MHz 대역의 무선 마이크용 송신기를 설계 및 제작하였다. 위상잡음을 고려한 주파수 합성기는 VCO, Loop Filter 및 RF 중폭부로 구성한 후 HP EEsof ADS ver. 1.3을 이용하여 설계하였다. VCO는 구조가 간단하며 변조가 용이한 직접변조방식을 사용하였으며 Loop Filter는 주파수 합성기의 기준 고조파 성분을 낮추기 위해 수동 3차 필터를 사용하였다. 주파수 대역 928.125 MHz～929.875 MHz 내에서 채널간격 125 kHz를 갖으며 15개의 채널이 되도록 분주비를 설정한 주파수 합성기는 제작 결과, 송신기 출력 9.3 dBm과 위상잡음이 100 kHz에서 -113 dBc/Hz 이하의 위상잡음 특성을 나타내었고 불요주파수 특성은 -80 dBc 이하의 특성을 나타내었다.

• Journal of Advanced Marine Engineering and Technology
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• 제30권3호
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• pp.444-448
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• 2006

In this paper, a frequency synthesizer for X-band FMCW radars is proposed. Some X-band FMCW radars have been used as a level sensor for tanker ship and the resolution of the level sensor may be mainly depend on linearity of frequency sweep. For a linear frequency sweep. the proposed synthesizer employs a phase-locked loop using prescalars and a high speed digital PLL chip. The measured results show that the linear frequency sweep range is from 10 GHz to 11 GHz and the output power of the synthesizer is minium 7 dBm. and the phase noise is about -80 dBc/Hz at 100 KHz offset from 11 GHz.

• 한국마린엔지니어링학회:학술대회논문집
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• 한국마린엔지니어링학회 2006년도 전기학술대회논문집
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• pp.109-110
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• 2006

The performance of a digital baseband signal processing and data transmission rate depends on the modulation technique. In this paper, We implemented DSP communication system for Underwater acoustic communication using by adaptive BPSK modem technique. In order to implement adaptive modem, we suggested SNR detection block. SNR detection block has the reference SNR value that selects between window filter path and matched filter path. In this paper, suggested system is based on software interface and all Hardware(PLL, modem filter, equalizer etc) is implemented by software, exclusive of DSP, A/D, D/A converter, SDRAM and Flash memory.

• JSTS:Journal of Semiconductor Technology and Science
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• 제13권4호
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• pp.282-290
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• 2013

This paper describes a spread spectrum clock generator (SSCG) circuit for DisplayPort 1.2 standard. A Hershey-Kiss modulation profile is generated by dual sigma-delta modulators. The structure generates various modulation slopes to shape a non-linear modulation profile. The proposed SSCG for DisplayPort 1.2 generates clock signals with 5000 ppm down spreading with a Hershey-Kiss modulation profile at three different clock frequencies, 540 MHz, 270 MHz and 162 MHz. The measured peak power reduction is about 15.6 dB at 540 MHz with the chip fabricated using a $0.13{\mu}m$ CMOS technology.

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 1990년도 한국자동제어학술회의논문집(국제학술편); KOEX, Seoul; 26-27 Oct. 1990
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• pp.1093-1097
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• 1990

A d.c. servomotor with pulse encoder is used to improve the movement of a hospital mobile robot along the desired line. We can achieve an improved movement of the robot by applying a PLL control. It is then shown that we can also reduce 42% of the power dissipation by the use of a PWM control. Furthermore, some simulation studies are presented to illustrate the design of PI control and optimal regulator for the control of the d.c. servomotor.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2001년도 하계종합학술대회 논문집(2)
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• pp.53-56
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• 2001

With the ever increasing clock frequency and integration level of CMOS circuits, I/O(input/output) and interconnect issues are becoming a growing concern. In this thesis, we propose the 2.5Gbps high speed input driver This driver consists of four different blocks, which are the high speed serializer , PECL(pseudo emitter coupled logic) Line Driver, PLL(phase lock loop) and pre-emphasis signal generator. The proposed pre-emphasis block will compensate the high frequency components of the 2.5Gbps data signal. Using the pre-emphasis block, we can obtain 2.5Gbps data signal with differential peak to peak voltage about 900 m $V_{p.p}$ This driver structure is on fabrication in 2.5v/10.25um 1poly, 5metal CMOS process.

• 전자공학회논문지B
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• 제32B권12호
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• pp.1644-1651
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• 1995

A data and clock recovery integrated circuit for MAC (Multiplexed Analog Component) TV standard is described. The chip performs the recovery of a system clock from a digitally encoded voice signal, clamping of a video signal for DC-level restoration, and precise gain control of a video signal in the presence of a large amplitude variation. A PLL (Phase Locked Loop) is used for timing recovery and a new gain control circuit is proposed which enhances its accuracy and dynamic range by employing two identical four-quadrant analog multipliers. The chip is designed in full custom with 1.5um BiCMOS technology, and layout verification is completed by post-simulation with the extracted circuit.

• 전자공학회논문지B
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• 제31B권9호
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• pp.67-75
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• 1994

In this paper, we manufactured the continuum receiver system for observing the continuum waves emitted from the continuum sources with using the 14m radio-telescope. The receiving system measures the total power of the continuum sources and consists of DC-amplifier, beam-chopper system. Phase-Locked Loop(PLL) circuit, blanking circuit and its period selection circuit, V/F converter, and counter part which are capable of interfacing with the computer which is used for a data acquisition and making the radio-telescope track the source. We compared the obsevation results which use the existing DVM method with the observation results which use the continuum receiver to measure the total power of the sources. Moreover, by method of beam switching observation which uses newly installed beam chopper system. We can significantly improve the observational efficiency more than the existing position switching observation method.

• 한국태양에너지학회 논문집
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• 제35권6호
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• pp.9-15
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• 2015

In this paper, a parallel operating technique for the stand alone photovoltaic (PV) power conditioning system (PCS) is proposed. The proposed parallel operating technique can increase the power rating of the system easily. Also, it provide three-phase connection function. The proposed technique does not separated master and slave system. Also, it does not use the separated synchronization line. Therefore, the PCS can supply continuous power even if one of the PCS breaks down. This technique is composed of a phase locked loop (PLL) control, droop control, current limit control and etc. Experimental result obtained on 2-kW prototype to verify the proposed technique.

• 한국광학회:학술대회논문집
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• 한국광학회 2009년도 창립 20주년기념 특별학술발표회
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• pp.241-242
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• 2009

Characterics of carrier-envelope-offset frequency ($f_{ceo}$) of a femtosecond laser stabilized by the direct locking method were investigated using two f-to-2f interferometers. The stability of $f_{ceo}$ was comaparable to that achieved with a conventional PLL method.