• 전력전자학회논문지
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• 제20권6호
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• pp.526-533
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• 2015

A new algorithm is proposed for the estimation of equivalent grid impedance at the point of common coupling of a grid-tie inverter output. The estimated impedance parameter can be used for the improvement of the performance and the stability of the distributed generation system. The estimation error is inevitable in the conventional estimation method because of the axis rotation due to PLL. In the conventional estimation error, the d-q voltage and current are used for the calculation of the impedance with active and reactive current injections. Conversely, in the proposed algorithm, the negative sequence current is injected, and then the negative sequence voltage is measured for the impedance estimation. As the positive and negative sequence current controller is independent and the PLL is based on the positive sequence component only, the estimation of the equivalent impedance can be achieved with high accuracy. Simulation and experimental results are compared to validate the proposed algorithm.

• 전력전자학회논문지
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• 제15권3호
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• pp.179-187
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• 2010

본 논문에서는 무효전력변동기법을 사용하여 단독운전을 검출을 하기 위해서 선행되어야 하는 주파수 검출 방법 중에서 개선된 이산푸리에변환(Discrete Fourier Transform; DFT), 즉 Goertzel 알고리즘을 이용한 단독운전 검출기법을 제안한다. 실제 태양광 발전 시스템의 설치를 위해서는 전기사고나 시스템에 악영향을 유발하는 단독운전 검출기법의 연구가 선행되어야 한다. 적용하는 주파수 검출방법은 Goertzel 알고리즘을 이용한 기법으로 기존의 영점검출기법과 가상의 2상 PLL(Phase Locked Loop)에 비하여 외란의 영향에 강인하며 빠른 검출이 가능하다. 시뮬레이션 및 실험을 통하여 기존의 주파수검출기법인 영점검출기법과 가상의 2상 PLL을 이용한 주파수 검출과 제안하는 알고리즘을 비교하고 그의 우수성을 검증하였다.

• 대한전기학회논문지:시스템및제어부문D
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• 제55권6호
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• pp.286-295
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• 2006

This paper presents a design of a real-time software GPS receiver which runs on a PC. The software GPS receiver has advantages over conventional hardware based receivers in terms of flexibility and efficiency in application oriented system design and modification. In odor to reduce the processing time of the software operations in the receiver, a shared memory structure is used with a dynamic data control, and the byte-type IF data is processed through an Open Multi-Processing technique in the mixer and integrator which requires the most computational load. A high speed data acquisition device is used to capture the incoming high-rate IF signals. The FFT-IFFT correlation technique is used for initial acquisition and FLL assisted PLL is used for carrier tracking. All software modules are operated in sequence and are synchronized with pre-defined time scheduling. The performance of the designed software GPS receiver is evaluated by running it in real-time using the real GPS signals.

• 조명전기설비학회논문지
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• 제12권1호
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• pp.51-57
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• 1998

본 논문은 구동신호 위상제어 기능을 갖는 SIT고주파공진 인버터를 제안하였다. SIT를 이용한 위상제어형인버터는 낮은 스위칭 손실로서 높은 스위칭 주파수의 전력변환을 실현시킬 수 있다. 특히 2단위 인버터의 출력전압을 직렬로 연결하여 높은 출력을 얻을 수 있다. 과전류에 대해서 보호회로를 이용한 시스템의 안정성과 그리고 PLL에 의해 부하변화에 따른 자동추종제어를 실현하였다. 특히 제안된 인버터는 고주파에서도 거의 정현파에 가까우며, 스위칭 주파수 범위는 180∼220〔kHz〕이고, 2〔kW〕의 유도가열에 응용하였다. 본 인버터의 동작 특성에 대해서 이론과 실험결과를 비교 검토하였다.

• 한국정보통신학회논문지
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• 제2권2호
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• pp.267-273
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• 1998

본 논문에서는 charge pump 회로를 차동 전류 스위치 구조를 갖는 회로를 사용하여 설계하였다. charge pump 회로의 스위칭 속도를 향상시키기 위하여 CMOS 보다 스위칭 속도가 빠른 MESFET를 이용하여 회로를 설계하였다. 차동 전류 스위치 구조의 charge pump회로가 고주파수 대역에서 동작하는데 따른 회로의 성능 및 안정성 문제를 제시하고 분석하였다. 또한 charge pump 회로의 성능을 평가하기 위한 척도를 세부적으로 정의함으로써 charge pump의 성능을 표현하게 된다. 설계된 회로는 HSPICE 시뮬레이터를 사용하여 시뮬레이션 하였으며, 시뮬레이션 결과 본 논문에서 제시한 구조가 1GHz급의 charge pump 회로로 설계가 가능하다는 것을 알 수 있었다.

• 한국정보통신학회논문지
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• 제18권9호
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• pp.2176-2182
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• 2014

이 논문에서는 기존의 위상고정루프에 전원 잡음 제거 회로를 추가한 위상고정 루프 회로를 제안한다. 제안한 구조는 주파수 전압 변환기를 변형한 전원 잡음 제거 회로를 사용하여 임의의 전원 잡음에 대해 보상하여 동작한다. 전원 잡음 제거 회로를 사용하여 전원 잡음에 의해 발생하는 지터의 크기를 1/3로 줄였다. 제안한 위상 고정 루프는 0.18um CMOS 공정을 사용 하여 HSPICE 시뮬레이션을 통해 예측되는 결과를 검증하였다.

• Journal of Power Electronics
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• 제12권6호
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• pp.886-894
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• 2012

This paper presents a secondary-side, dual-mode feedback LLC resonant controller IC with dynamic PWM dimming for LED backlight units. In order to reduce the cost, master and slave outputs can be generated simultaneously with a single LLC resonant core based on dual-mode feedback topologies. Pulse Frequency Modulation (PFM) and Pulse Width Modulation (PWM) schemes are used for the master stage and slave stage, respectively. In order to guarantee the correct dual feedback operation, Phased-Locked Loop (PLL)-based automatic duty control circuit is proposed in this paper. The chip is fabricated using $0.35{\mu}m$ Bipolar-CMOS-DMOS (BCD) technology, and the die size is $2.5mm{\times}2.5mm$. The frequency of the gate driver (GDA/GDB) in the clock generator ranges from 50 to 425 kHz. The current consumption of the LLC resonant controller IC is 40 mA for a 100 kHz operation frequency using a 15 V supply. The duty ratio of the slave stage can be controlled from 40% to 60% independent of the frequency of the master stage.

• Journal of Power Electronics
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• 제13권3호
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• pp.487-496
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• 2013

The three-phase synchronous reference frame phase-locked loop (SRF-PLL) is widely used for synchronization applications in power systems. In this paper, a new control strategy for three-phase grid-connected LCL inverters without a PLL is presented. According to the new strategy, a current reference can be generated by using the instantaneous power control scheme and the proposed positive-sequence voltage detector. Through theoretical analysis, it is indicated that a high-quality grid current can be produced by introducing the new control strategy. In addition, a kind of independent control for reactive power can be achieved under unbalanced and distorted grid conditions. Finally, the excellent performance of the proposed control strategy is validated by means of simulation and experimental results.

• 전기학회논문지
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• 제64권12호
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• pp.1709-1717
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• 2015

In remote islands PV (Photo Voltaic) panel with BESS (Battery Energy Storage System) supplies electric power to the customers in parallel operation with EG (Engine Generator) to save fuel consumption and to mitigate environmental load. BESS operates in voltage control mode when it supplies power to the load alone, while it operates in current control mode when it supplies power to the load in parallel with EG. This paper proposes a smooth mode change scheme from current control to voltage control of BESS by adding proper initial value to the integral part of voltage control, and a smooth mode change scheme from voltage control to current control by tracking the EG output voltage to the BESS output voltage using PLL (Phase-Locked Loop). The feasibility of proposed schemes was verified through computer simulations with PSCAD/EMTDC, and the feasibility of actual hardware system was verified by experiments with scaled prototype. It was confirmed that the proposed schemes offer a seamless operation in the stand-alone power system in remote islands.

• 전기학회논문지
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• 제63권10호
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• pp.1467-1472
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• 2014

This paper study on powering characteristic on speed variation of propulsion system of prototype 8200 electric locomotive propulsion system through simulation modeling. For this purpose, it being applied in the field of railway IGBT (Insulated Gate Bipolar Transistor) elements are used. Converter was performed PLL (Phase-Locked Loop) control method that is used to control the phase and output voltage, and the inverter was carried an indirect vector control method to control the speed of traction motor. The results of simulation by modeling and experimental unit, we was confirmed that converter is controlled a unity power factor and output voltage by reference voltage. Also traction motor was controlled by indirect vector control and SVPWM inverter switching method very well.