• The Transactions of the Korean Institute of Electrical Engineers P
• /
• v.54 no.3
• /
• pp.111-118
• /
• 2005

Since the residential load is an AC load and the output of solar cell is DC power, the photovoltaic system needs the DC/AC converter to utilize solar cell. In case of driving to interact with utility line, in order to operate at unity power factor, converter must provide the sinusoidal wave current and voltage with same phase of utility line. Since output of solar cell is greatly fluctuated by insolation, it is necessary that the operation of solar cell output in the range of the vicinity of maximum power point. In this paper, DC/AC converter is three phase PWM converter with smoothing reactor. And then, feed-forward control used to obtain a superior characteristic for current control and digital PLL circuit used to detect the phase of utility line.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.45 no.4
• /
• pp.21-26
• /
• 2008

In this paper, a novel 622Mbps burst-mode clock and data recovery (CDR) circuit is proposed for passive optical network (PON) applications. The CDR circuits are implemented with 0.35um CMOS process technology. Locking dynamics is accomplished with instantaneous feature and data are sampled at an optimal timing. This is realized by seven different delay configurations, which are generated from precisely-controlled delay buffers. The experimental results show that the proposed CDR circuits are operating as expected, recovering an incoming 622Mbps burst-mode input data without errors.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
• /
• v.19 no.6
• /
• pp.100-108
• /
• 2005

In this paper deals with the frequency control of the HVDC scheme linking Haenam to Cheju Island. The primary aim of the study is to develop and evaluate a new frequency control that can be employed without having to utilise the existing Synchronous Compensators(Gas Turbines). Transient condition studies are performed utilising the detailed control strategies for the HVDC link, implemented in PSCAD/EMTDC. Study cases are completed involving synchronous compensators trip and load ripping events and study plots presented. It is demonstrated that the existing frequency measurement can be replaced by one derived from the AC network alone, incorporated into a new frequency control algorithm and gives effective frequency control and dynamic performance.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.15 no.7
• /
• pp.1552-1558
• /
• 2011

In this paper, a dual-loop Integer-N phase-delay locked loop(P DLL) architecture has been proposed using a low power consuming voltage controlled delay line(VCDL). The P DLL can have the LF of one small capacitance instead of the conventional second or third-order LF which occupies a large area. The proposed dual-loop P DLL can have a small gain VCDL by controlling the magnitude of capacitor and charge pump current on the loop of VCDL. The proposed dual-loop P DLL has been designed based on a 1.8V $0.18{\mu}m$ CMOS process and proved by Hspice simulation.

• Journal of Power Electronics
• /
• v.18 no.5
• /
• pp.1523-1535
• /
• 2018

High-performance Phase-Locked Loops (PLLs) are critical for grid synchronization in grid-tied power electronic applications. In this paper, a new single-phase All Digital Phase-Locked Loop (ADPLL) is proposed. It features fast transient response and good robustness under distorted grid conditions. It is designed for Field Programmable Gate Array (FPGA) implementation. As a result, a high sampling frequency of 1MHz can be obtained. In addition, a new OSG is adopted to track the power frequency, improve the harmonic rejection and remove the dc offset. Unlike previous methods, it avoids extra feedback loop, which results in an enlarged system bandwidth, enhanced stability and improved dynamic performance. In this case, a new parameter optimization method with consideration of loop delay is employed to achieve a fast dynamic response and guarantee accuracy. The Phase Detector (PD) and Voltage Controlled Oscillator (VCO) are realized by a Coordinate Rotation Digital Computer (CORDIC) algorithm and a Direct Digital Synthesis (DDS) block, respectively. The whole PLL system is finally produced on a FPGA. A theoretical analysis and experiments under various distorted grid conditions, including voltage sag, phase jump, frequency step, harmonics distortion, dc offset and combined disturbances, are also presented to verify the fast dynamic response and good robustness of the ADPLL.

• The Transactions of the Korean Institute of Electrical Engineers P
• /
• v.59 no.2
• /
• pp.135-140
• /
• 2010

This paper presents a sensorless speed control of BLDC Motor using terminal voltage of the one phase. Rotor position information is extracted by indirectly sensing the back EMF from only one of the three terminal voltages for a three-phase BLDC motor. Depending on the terminal voltage sensing rotor position, active filter is used for position information. This leads to a significant reduction in the component device of the sensorless circuit. Therefore this is a advantage for the cost saving and size reduction. With indirect sensing methods based on detection of the terminal voltage that require active filtering, the position information needs the six divider section by PLL circuit, the binary counter and johnson counter by the EPLD. Finally, this algorithm can estimate the rotor position information similar to Hall-sensor sticked the three-phase BLDC motor. As a result, the method described that it is not sensitive to filtering delays, allowing the motor to achieve a good performance over a wide speed range. In addition, a simple starting method and a speed estimation approach are also proposed. Experimental and simulation results are included to verify the proposed scheme.

• The Korean Journal of Physiology and Pharmacology
• /
• v.8 no.6
• /
• pp.329-333
• /
• 2004

In this study, we investigated whether TNF-alpha, IL-1beta, CTMA (carboxymethyl trimethylammonium) and LPD (Lup-20[29]-ene-3beta,28-diol) affect mucin release from airway goblet cells and compared the activities of these agents with the inhibitory action of PLL and the stimulatory action of ATP on mucin release. Confluent primary hamster tracheal surface epithelial (HTSE) cells were metabolically radiolabeled with $^3H-glucosamine$ for 24 h and chased for 30 min in the presence of varying concentrations of each agent to assess the effects on $^3H-mucin$ release. The results were as follows: TNF-alpha, CTMA and LPD increased mucin release at the highest concentration, but IL-1beta did not. We conclude that CTMA and LPD can stimulate mucin release by directly acting on airway mucin-secreting cells, and suggest that these agents should be further investigated for the possible use as mild expectorants during the treatment of chronic airway diseases.

• The Transactions of the Korean Institute of Power Electronics
• /
• v.10 no.5
• /
• pp.457-467
• /
• 2005

This paper deals with the new frequency controller of the HVDC scheme linking Haenam to Cheju Island. The primary aim of the study is to develop and evaluate a new frequency controller after the removing of the present synchronous compensators. The simulation methods are the mix of PSCAD/EMTDC and PSS/E, the main system studies are done for the transient state analysis using PSCAD/EMTDC. The study cases are completed involving 3 phase, single phase trip and load tripping events and study plots presented. In conclusion, the new frequency measurement from the AC network gives effective frequency control and dynamic performance.

• Proceedings of the KIPE Conference
• /
• 2004.07a
• /
• pp.133-136
• /
• 2004

Since the residential load is an AC load and the output of solar cell is a DC power, the photovoltaic system needs the DC/AC converter to utilize solar cell. In case of driving to interact with utility line, in order to operate at unity power factor, converter must provide the sinusoidal wave current and voltage with same phase of utility line. Since output of solar cell is greatly fluctuated by insolation, it is necessary that the operation of solar cell output in the range of the vicinity of maximum power point. In this paper, DC/AC converter is three phase PWM converter with smoothing reactor. And then, feedforward control used to obtain a superior characteristic for current control and digital PLL circuit used to detect the phase of utility line.

• Proceedings of the KIEE Conference
• /
• 2006.10c
• /
• pp.394-396
• /
• 2006

When developing a new GPS receiver module, the essential problems are evaluation of reliable algorithms, software debugging, and performance comparison between algorithms to find optimal solution. Most GPS receiver modules nowadays use a correlator to track signals from satellites and an MCU (Micro Controller Unit) to control operations of the entire module. The problem of software evaluation from MCU is very difficult, due to limitation of MCU resources and low ability of interfacing with user. Normally, user has to expense special tool kit for a limiting access to MCU but it is also hard to use. This article introduces an implementation of a GPS receiver test bed using correlator GP2021 interfacing with ISA (Industry Standard Architecture) PC bus. This way can give user complete control and visibility into the operation of the receiver, then user can easily debug program and test algorithms. For this article, the least square method is implemented to test the hardware and software performance.