• The Journal of Korean Institute of Communications and Information Sciences
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• v.37 no.6C
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• pp.502-511
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• 2012

As the importance of GNSS system increases, the necessity of independent system is increased also. When the independent GNSS system is required, GNSS signal design is necessary with requirement definition. This paper suggests the design method of GNSS signal using the analysis result of receiver performance. First, the candidates are defined based on the design elements. Then the receiver performance of the candidates is analyzed based on the performance evaluation parameters. The weights of performance evaluation parameter are defined in order to consider the receiver performance in a various aspects. Finally, the calculation of normalized performance evaluation parameters and weights are derived to obtain the compared value for signal selection. Spreading code, modulation method and carrier frequency are considered as design parameters. Also, correlation width, DLL PLL thermal noise jitter, frequency bandwidth and side lobe peak ratio are considered as performance evaluation parameters. And positioning performance, robustness to noise, bandwidth efficiency are considered as the performance aspects. This paper analyzes the performance of each candidate using software based simulator and suggest the method to compare objectively the performance of each candidates.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.2
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• pp.94-99
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• 2010

This paper presents a charge pump architecture for correcting the current mismatch due to the PVT variation. In general, the current mismatch of the charge pump should be minimized to improve the phase noise and spur performance of the PLL. In order to correct the current mismatch of the charge pump, the current difference is detected by the replica charge pump and fed back into the main charge pump. This scheme is very simple and guarantees the high accuracy compared with the prior works. Also, it shows a good dynamic performance because the mismatch is corrected continuously. It is implemented in 0.13um CMOS process and the die area is $100{\mu}m\;{\times}\;160{\mu}m$. The voltage swing is from 0.2V to 1V at supply voltage of 1.2V. The charging and discharging currents are $100{\mu}A$, respectively and the current mismatch due to the PVT variation is less than 1%.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.32 no.1A
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• pp.83-90
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• 2007

In this paper, we propose an implementation and an algorithm of 'Jitter and Glitch Removing Circuit' for UHF RFID reader system based on ISO/IEC 18000-6C standard. We analyze the response of TI(Texas Instrument) Gen2 tag with a reader using the proposed algorithm. In ISO/IEC 18000-6C standard, a bit rate accuracy(tolerance) is up to +/-22% during tag-to-interrogator communication and +/-1% during interrogator-to-tag communication. In order to solve tolerance problems, we implement the Jitter and Glitch Removing Circuit using the concept of tolerance and tolerance-accumulation instead of PLL(DPLL, ADPLL). The main clock is 19.2MHz and the LF(Link Frequency) is determined as 40kHz to meet the local radio regulation in korea. As a result of simulations, the error-rate is zero within 15% tolerance of tag responses. And in the case of using the adaptive LF generation circuit, the error-rate varies from 0.000589 to zero between 15% and 22% tolerance of tag responses. In conclusion, the error-rate is zero between 0%-22% tolerance of tag response specified in ISO/IEC 18000-6C standard.

• Proceedings of the KIEE Conference
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• 2002.07b
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• pp.990-992
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• 2002

30kW electrical power conversion system is delveloped for the variable speed wind turbine system. In the wind energy conversion system(WECS) a synchronous generator with field current excitation converts the mechanical energy into electrical energy. As the voltage and frequency of generator output vary according to the wind speed, a dc/dc boosting chopper is utilized to maintain constant dc link voltage. Grid connection type PWM inverter supply currents into the utility line by regulating the dc link voltage. The active power is controlled by q-axis current which the reactive power can be controlled by d-axis current reference change. The phase angle of utility voltage is detected using s/w PLL(Phased Locked Loop) in d-q synchronous reference frame. This scheme gives a low cost power solution for variable speed WECS.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.46 no.8
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• pp.1-9
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• 2009

In this paper, we describe DSSS transceiver development robust to jamming signals as an investigation of ECCM transceiver for UAV uplink. The jamming margin is 15dB or greater with the development target of transceiver because the jamming margin is more important than the transmission rate of data and the spreading code can be changeable. The rake receiver is applied to combine multipath components and turbo code which the coding gain is 7.2dB as a FEC. In this paper, the whole structure, design method and functional test result about the designed modem are described and a conclusion is made.

• 제어로봇시스템학회:학술대회논문집
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• 2003.10a
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• pp.1016-1021
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• 2003

The overall size of electronic product is becoming small according to development of technology. Accordingly it is difficult to inspect these small components by human eyes. So, an automation system for inspecting them has been used. The existing system put microprocessor or Programmable Logic Controller (PLC) use. The structure of microprocessor-based controller and PLC use basically composed of memory devices such as ROM, RAM and I/O ports. Accordingly, the system is not only becomes complicated and enlarged but also higher price. In this paper, we implement FPGA-based One-chip Programmable Timing Controller for Inspecting Small components to resolve above problems and design the high performance controller by using VHDL. With fast development, the FPGA of high capacity that can have memory and PLL have been introduced. By using the high-capacity FPGA, the peripherals of the existent controller, such as memory, I/O ports can be implemented in one FPGA. By doing this, because the complicated system can be simplified, the noise and power dissipation problems can be minimized and it can have the advantage in price. Since the proposed controller is organized to have internal register, counter, and software routines for generating timing signals, users do not have to problem the details about timing signals and need to only send some values about an inspection system through an RS232C port. By selecting theses values appropriate for a given inspection system, desired timing signals can be generated.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.6
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• pp.51-56
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• 2010

In this paper, a novel Integer-N phase-delay locked loop(P DLL) architecture has been proposed using a voltage controlled delay line(VCDL). The P DLL can have the LF of one small capacitance instead of the conventional second or third-order LF. The size of chip is $255{\mu}m$ $\times$ $935.5{\mu}m$ including the LF. The proposed P DLL has been designed based on a 1.8V $0.18{\mu}m$ CMOS process and proved by HSPICE simulation.

• Proceedings of the KIPE Conference
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• 2016.07a
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• pp.83-84
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• 2016

본 논문은 3상 계통 연계형 인버터의 seamless transfer 를 위한 비례공진 제어기를 활용한 간접 전류 제어 기반의 모드 절환 기법에 대해 다루고 있다. 분산 발전 기반의 인버터는 계통 연계 모드와 독립 운전 모드에서 각각 전류원과 전압원으로서 정의된다. 이런 이유로 계통 연계형 인버터는 두 모드 영역에서 고품질의 전력을 공급하기 위한 신뢰할 만한 제어기를 필요로 한다. 따라서 기존에 두 모드 모두에서 사용 가능한 PR 제어 기반의 간접 전류 제어기가 제안되었다. 하지만 추가적으로 분산 발전 기반의 인버터 전원 공급의 신뢰성은 각 모드의 절환시에도 마찬가지로 유지되어야 할 필요성을 가진다. 따라서 본 논문에서는 독립운전에서 계통 연계 모드로 절환 시 필요 되어지는 PLL 모드에서의 PR 제어 기반의 모드 절환 기법에 대하여 제안한다. 최종적으로 인버터의 정상상태뿐만 아니라 과도 상태에서 지역적 부하와 계통 모두에 신뢰할 만한 전력을 공급하기위해 제안된 PR 제어 기반의 모드절환방식은 PSIM 시뮬레이션을 통해 seamless transfer 를 구현할 수 있음이 입증되었다.

• 한국정보디스플레이학회:학술대회논문집
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• 2004.08a
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• pp.673-675
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• 2004

This study proposes controller with voltage-compensated drivers for producing gray-scaled pictures on passive matrix organic light emitting diodes (PMOLEDs) panels. The controller includes voltage type drivers so the output impedance of the driver is far less than that of the current-type driver. Its low output impedance provides better electron-optical properties than those of traditional current drivers. A free running clock and a group of counters are applied to the gray-scaled function so that phase lock loop (PLL) circuit can be reduced in the controller. A pre-charge function is used to enhance performance of the luminance of an active OLED pixel. As a result, distribution of the low gray level portion is achieved linear relationship with input data. In this work, the digital part of the proposed controller is implemented using FPGA chips, and analog parts are combined with a digital-analog converter (DAC) and analog switches. A still image is displayed on a $48^{\ast}64$ PMOLEDs panel to assess the luminance performance fir the controller. Based on its cost requirement and luminance performance, the controller is qualified to join the market for driving PMOLEDs panels.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.06a
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• pp.401-401
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• 2009

Recently, demands for the development of compact, lightweight power supplies with higher power density and higher efficiency have been increased. Since Piezoelectric Transformer (PT) was emerged in device and material industry, it has been suggested as a viable alternative to the magnetic transformer in some applications. PT has some advantages such as low profile and mechanical energy transfer with little electromagnetic interface (EMI). Also, PT can provide high voltage stepping ratio with good isolation and requires no copper windings saving copper usage especially for large voltage conversion differences. Conventional control of PT converter has mainly two-way. One is the pulse frequency modulation (PFM) control method and the other is the pulse width modulation (PWM) control with frequency fixed method. It is known that the maximum PT efficiency can be obtained when it operates near the resonant frequency of the PT. And, also PT's resonant frequency moves according to the load condition. Therefore, selection of PT converter control method is very difficult. This paper analyzes general piezo-electric converter modeling and proposes a guide-line to selection of control method and stabilization control.