• Proceedings of the KIPE Conference
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• 2008.06a
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• pp.164-166
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• 2008

Ultrasonic welder joins with a horn and a booster for amplification of the mechanical displacement. This coupling generates other resonance points at a frequency range lower than the piezoelectric material's resonance frequency. Therefore, frequency variation range through PLL control was proposed in order to prevent reaction to these resonance points.

• Proceedings of the KIEE Conference
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• 1987.07b
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• pp.950-953
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• 1987

A wave difference method(WDH) phase detector for timing recovery is designed in the digital subscriber loop receiver. This paper describes the architecture and experimental results of the WDM, tankless timing extraction PLL. The results show that the designed WDM timing extraction circuit have stable jitter performance without the use of high precision LC tank circuit.

• Proceedings of the KIPE Conference
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• 2012.11a
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• pp.109-110
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• 2012

본 논문에서는 불평형 전원 전압 하에서 삼상 PWM 컨버터의 전류 보상 기법을 제안하였다. 전원 전압이 불평형인 경우 PLL(Phase Locked Loop)를 이용하여 추출한 위상각에는 왜곡 성분이 포함된다. 이러한 왜곡된 위상각으로 컨버터를 제어하는 경우 입력 전류에도 고조파가 포함되게 된다. 본 논문에서는 불평형 전원 전압 하에서도 입력 전류의 THD(Total Harmonic Distortion)를 IEEE Std. 519 규정인 5% 이내로 제한할 수 있도록 하는 전류 보상 기법을 제안하였다. 제안된 기법은 시뮬레이션을 통해 그 타당성을 검증하였다.

• Journal of information and communication convergence engineering
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• v.6 no.1
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• pp.47-50
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• 2008

A novel high channel efficiency transceiver based on a fast acquisition frequency synthesizer has been designed. The direct digital synthesis (DDS) technique is applied and a simple memory look-up table is incorporated to expedite channel acquisition. The technique simplifies the frequency control process in the transceiver and thus reduces the channel switching time. As a result, the channel efficiency is improved. The designed transceiver is ideal for frequency hopping mobile communication applications.

• Proceedings of the KIPE Conference
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• 1999.07a
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• pp.671-674
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• 1999

In the PWM converter, PLL(Phase Locked Loop) is usually used as a tool which senses the angle of input voltage. This is sensitive to nois and needs additional hardware. In this work, we propose a sensorless control scheme of PWM converter using EKF(Extended Kalman Filter). EKF estimates a phase angle of input voltage from nonlinear state equation using measured phase currents. We control power factor and DC-link voltage utilizing the estimated phase angle. We demonstrate the effectiveness of the proposed estimation algorithm through simulations.

• Proceedings of the KIPE Conference
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• 1999.07a
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• pp.122-125
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• 1999

The AC-to-DC single-phase PWM rectifier for traction applications using high power semiconductor, IGCT is made and tested. Parallel operation of two PWM converter is adopted for increasing capacity of converters. For reducing harmonics, the harmonic content is eliminated by the phase shift between two converters switching phase. The output voltage control is achieved by interns calculation without detecting the input current. The part of PLL used for controlling power factor is simply implemented by software.

• Proceedings of the IEEK Conference
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• 2000.11b
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• pp.212-215
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• 2000

This paper introduces to design analog circuits with Verilog-A. It is a tool for design and simulation of analog ICs in behavioral level. Verilog-A has been already established standard and used to IP development in USA. We have proved the possibility of Verilog-A by comparing with measurement data of a fabricated 235MHz PLL circuit. This paper also describes another advantage of Verilog-A.

• The Journal of the Acoustical Society of Korea
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• v.5 no.3
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• pp.44-49
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• 1986

회로의 간편성에 최대 역점을 두어 PLL을 이용한 정현파 간섭음을 실시간으로 제거하는 방식을 제안하였다. SC 여파기를 이용한 적응 노치 여파기ㅘ 적응 대역 여파기를 자기 동조법으로 구동시킴으 로써 간섭음을 제거하였다. SC 여파기의 구동 스위칭 주파수는 제거하려는 신호 주파수으 L49배가 되 도록 하엿으며 소자의 동작 특성상 4KHz의 간섭음 제거 대역을 갖게 된다. 노치 여파기는 6차 여파기 이고 감쇄도는 중심 주파수에서 약 -56dB이다.

• Proceedings of the IEEK Conference
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• 2001.06b
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• pp.81-84
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• 2001

In recent years, the design of CMOS VCO at ever-higher frequencies has gained interest. This paper proposes an arithmetic functionality VCO circuit based on a differential ring oscillator for operating in high frequency. The proposed VCO architecture with half adder is able to produce two times higher frequency with my delay cell than conventional VCO produce double oscillation frequency and power dissipation is 14.59mW.

• Proceedings of the IEEK Conference
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• 1999.11a
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• pp.271-274
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• 1999

This paper proposes a simple architecture of digital dividing block in dual-modulus prescaler phase-locked loop used in the wireless communication. Proposed architecture eliminates a swallow counter in the conventional one and demonstrates the advantages in reducing the power consumption and the gate-counts. Therefore, it is suitable for small die area and low power applications. The circuit is designed in a standard 0.35${\mu}{\textrm}{m}$ CMOS process.