• Title/Summary/Keyword: PLL

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Implementation algorithm and system for generating PWM frequency for berthing the train at station (열차의 정위치 정차용 주파수의 PWM 생성 알고리즘과 시스템 구현)

  • Eun-Taek Han;Chang-Sik Park;Ik-Jae Kim;Dong-Kyoo Shin
    • Journal of Internet Computing and Services
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    • v.24 no.5
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    • pp.37-50
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    • 2023
  • In general, PLL or DDS are mainly used as precise and stable frequency synthesis methods. For stable operation, a PWM frequency generation algorithm was designed and implemented using FPGA. This is an algorithm that creates a frequency 8,192 times the target frequency and then performs the D flip-flop 13 times to generate multiple frequencies with a precision of 1 Hz. Using the designed algorithm, it is applied to the Berthing system for stopping trains in station. The applied product was developed and tested against the existing operating system to confirm its superior performance in terms of frequency generation accuracy.

121.15MHz Frequency Synthesizers using Multi-phase DLL-based Phase Selector and Fractional-N PLL (다중위상 지연고정루프 기반의 위상 선택기와 분수 분주형 위상고정루프를 이용하는 121.15 MHz 주파수 합성기)

  • Lee, Seung-Yong;Lee, Pil-Ho;Jang, Young-Chan
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.17 no.10
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    • pp.2409-2418
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    • 2013
  • Two frequency synthesizers are proposed to generate a clock for a sub-sampler of an on-chip oscilloscope in this paper. These proposed frequency synthesizers are designed by using a multi-phase delayed-locked loop (DLL)-based phase selector and a fractional-N phase-locked loop (PLL), and they are analyzed by comparing simulation results of each frequency synthesizer. Two proposed frequency synthesizers are designed using a 65-nm CMOS process with a 1V supply and output the clock with the frequency of 121.15 MHz when the frequency of an input clock is 125 MHz. The designed frequency synthesizer using a multi-phase DLL-based phase selector has the area of 0.167 $mm^2$ and the peak-to-peak jitter performance of 2.88 ps when it consumes the power of 4.75 mW. The designed frequency synthesizer using a fractional-N PLL has the area of 0.662 $mm^2$ and the peak-to-peak jitter performance of 7.2 ps when it consumes the power of 1.16 mW.

Design of a CMOS Dual-Modulus Prescaler Using New High-Speed Low-Power TSPC D-Flip Flops (새로운 고속 저전력 TSPC D-플립플롭을 사용한 CMOS Dual-Modulus 프리스케일러 설계)

  • Oh, Kun-Chang;Lee, Jae-Kyong;Kang, Ki-Sub;Park, Jong-Tae;Yu, Chong-Gun
    • Journal of IKEEE
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    • v.9 no.2 s.17
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    • pp.152-160
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    • 2005
  • A prescaler is an essential building block for PLL-based frequency synthesizers and must satisfy high-speed and low-power characteristics. The design of D-flip flips used in the prescaler implementation is thus critical. Conventional TSPC D-flip flops suffer from glitches, unbalanced propagation delay, and unnecessary charge/discharge at internal nodes in precharge phase, which results in increased power consumption. In this paper a new dynamic D-flip flop is proposed to overcome these problems. Glitches are minimized using discharge suppression scheme, speed is improved by making balanced propagation delay, and low power consumption is achieved by removing unnecessary discharge. The proposed D-flip flop is employed in designing a 128/129 dual-modulus prescaler using $0.18{\mu}m$ CMOS process parameters. The designed prescaler operates up to 5GHz while conventional one can operate up to 4.5GHz under same conditions. It consumes 0.394mW at 4GHz that is a 34% improved result compared with conventional one.

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Comparative Analysis on Disc Resorption Rate of Lumbar Disc Herniation Patients after Korean Medicine Treatment and Predictive Factors Associated with Disc Resorption (요추 추간판 탈출증 환자의 한의치료 후 디스크 흡수율 비교 및 흡수에 영향을 주는 요인 분석 연구)

  • Kim, Yong-Hyeon;Lee, Ju-Young;Kim, Kwang-Hwi;Kim, Tae-Yeon;Lee, Tae-Geol;Lee, Sang-Woon;Chu, Hui-Yeong;Jeong, Hui-Gyeong
    • Journal of Korean Medicine Rehabilitation
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    • v.28 no.4
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    • pp.33-41
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    • 2018
  • Objectives The purpose of this study is to analyze the effects of Korean Medicine treatment on lumbar disc herniation (LDH) and predictive factors associated with disc resorption by magnetic resonance imaging (MRI). Methods A retrospective study was carried out in 79 lumbar disc herniation patients who had visited Haeundae Jaseng Hospital of Korean Medicine. Patients' diagnosis was based on MRI. MRI was performed on two or more occasions and patients were received Korean Medicine treatment within the period. The volume of each herniated disc was measured three-dimensionally and patient characteristics, interval between MRIs, herniated disc level, disc herniation type, disc migration, intactness of posterior longitudinal ligament (PLL), initial volume of herniated disc, modic change, disc resorption rate were statistically analyzed. Results The mean volumes of herniated discs before Korean Medicine treatment and after Korean Medicine treatment were $1,547.81{\pm}598.15mm^3$ and $947.06{\pm}335.28mm^3$, respectively. The mean resorption rate was $35.7{\pm}16.3%$. Disc extent, intactness of PLL and initial volume of herniated discs were significantly correlated with resorption rate (p=0.003, p=0.001 and p=0.024, respectively). Conclusions Korean Medicine treatment is an effective conservative treatment for lumbar disc herniation. Factors such as disc migration, intactness of PLL, initial volume of herniated disc have a significant association with disc resorption rate.

A Charge Pump Circuit in a Phase Locked Loop for a CMOS X-Ray Detector (CMOS X-Ray 검출기를 위한 위상 고정 루프의 전하 펌프 회로)

  • Hwang, Jun-Sub;Lee, Yong-Man;Cheon, Ji-Min
    • The Journal of Korea Institute of Information, Electronics, and Communication Technology
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    • v.13 no.5
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    • pp.359-369
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    • 2020
  • In this paper, we proposed a charge pump (CP) circuit that has a wide operating range while reducing the current mismatch for the PLL that generates the main clock of the CMOS X-Ray detector. The operating range and current mismatch of the CP circuit are determined by the characteristics of the current source circuit for the CP circuit. The proposed CP circuit is implemented with a wide operating current mirror bias circuit to secure a wide operating range and a cascode structure with a large output resistance to reduce current mismatch. The proposed wide operating range cascode CP circuit was fabricated as a chip using a 350nm CMOS process, and current matching characteristics were measured using a source measurement unit. At this time, the power supply voltage was 3.3 V and the CP circuit current ICP = 100 ㎂. The operating range of the proposed CP circuit is △VO_Swing=2.7V, and the maximum current mismatch is 5.15 % and the maximum current deviation is 2.64 %. The proposed CP circuit has low current mismatch characteristics and can cope with a wide frequency range, so it can be applied to systems requiring various clock speed.

A Study to Improve the DC Output Waveforms of AFE Three-Phase PWM Rectifiers (AFE 방식 3상 PWM 정류기의 직류 출력파형 개선에 관한 연구)

  • Jeon, Hyeon-Min;Yoon, Kyoung-Kuk;Kim, Jong-Su
    • Journal of the Korean Society of Marine Environment & Safety
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    • v.23 no.6
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    • pp.739-745
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    • 2017
  • Many studies have been conducted to reduce environmental pollution by ships and reduce fuel consumption. As part of this effort, research on power conversion systems through DC distribution systems that link renewable energy with conventional power grids has been pursued as well. The diode rectifiers currently used include many lower harmonics in the input current of the load and distort supply voltage to lower the power quality of the whole system. This distortion of voltage waveforms causes the malfunctions of generators, load devices and inverter pole switching elements, resulting in a large number of switching losses. In this paper, a controller is presented to improve DC output waveforms, the input Power Factor and the THD of an AFE type PWM rectifier used for PLL. DC output voltage waveforms have been improved, and the input Power Factor can now be matched to the unit power factor. In addition, the THD of the input power supply has been proven by simulation to comply with the requirements of IEEE Std514-2014.

Laser Doppler Vibrometer with Self Vibration Compensation (자체 진동 보상기능을 가진 레이저 도플러 진동측정계에 관한 연구)

  • Lee, Young-Jin;Kim, Ho-Seong
    • Proceedings of the KIEE Conference
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    • 2001.11a
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    • pp.53-55
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    • 2001
  • A dual probe laser Doppler vibrometer (LDV) that has one laser source and provides two independent object beams has been developed for the first time. An electronic circuit that converts light signal to electronic signal has been also developed using phase locked loop(PLL). It was found that this types of dual probe LDV can be used in differential mode and self-vibration compensation mode.

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Design of Charge pump for Removing Spur by Input Reference (기준입력신호로 인한 Spur 제거용 차지펌프 설계)

  • 이준호;김선홍;김영랄;김재영;김동용
    • Proceedings of the IEEK Conference
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    • 2000.06b
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    • pp.209-212
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    • 2000
  • Charge pump based upon a phase locked loop(PLL) is described. This charge pump show that it is possible to overcome the issue of charge pump current mismatch by using a current subtraction circuit. Also, this charge pump can suppress reference spurs and disturbance of the VCO control voltage. HSPICE simulations are performed using 0.25$\mu\textrm{m}$ CMOS process.

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Digital signal processing of automatic frequency control is VCR (비디오 카세트 레코더의 자동 주파수 조절의 디지탈 신호처리)

  • 김동하;이태원
    • Journal of the Korean Institute of Telematics and Electronics B
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    • v.33B no.6
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    • pp.128-135
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    • 1996
  • In this paper, a digital signal processing method of AFC (automatic frequency control) is proposed for a home use VCR system. The proposed method has the ability of frequency tracking of a wide range. Implemented with digital circuits, the system is to be used in a digital video system and saves the cost of a hardware compared with a conventional analog automatic frequency control method using several PLL's in case of making home use VCR systems compatible with several TV systems.

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Magnetic Resistance Angle Sensor Ripple Elimination Method Using Phase Locked Loop (위상동기루프를 이용한 자기저항 각도 센서의 맥동 제거 방법)

  • Lee, Jeonghun;Kim, Sungjin;Nam, Kwanghee
    • Proceedings of the KIPE Conference
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    • 2016.07a
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    • pp.523-524
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    • 2016
  • 본 논문에서는 자기저항 (Magnetic Resistive, MR)각도 센서에서 자속 간섭 및 축 진동과 같은 외란에 의해 발생하는 각도맥동을 해결하는 방법이 연구되었다. 외란에 의한 각도 맥동은 일정한 기계각 속도 한 주기 내에서 전기각 속도가 불균일하게 측정되는 현상이다. 이를 해결하기 위해 위상동기루프 (phase locked loop, PLL)를 적용하였고, 자기저항 각도 센서의 각도 맥동을 효과적으로 제거하였다.

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