• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2011.05a
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• pp.129-131
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• 2011

An 6.4-Gb/s/channel 4-PAM transceiver is designed for a high speed memory application. The asymmetric 4-PAM signaling scheme is proposed to increase the voltage and time margins, and reduces the reference noise effect in a receiver by 33%. To reduce ISI in a channel, 1-tap pre-emphasis of a transmitter is used. The proposed asymmetric 4-PAM transceiver was implemented by using 0.13um 1-poly 6-metal CMOS process with 1.2V supply. The active area and power consumption of 1-charmel transceiver including a PLL are $0.294um^2$ and 6mW, respectively.

• Journal of Communications and Networks
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• v.7 no.3
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• pp.248-257
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• 2005

In this paper, we develop design procedures for carrier tracking loop for orthogonal frequency division multiplexing (OFDM) systems or other systems of blocked data. In such communication systems, phase error measurements are made infrequent enough to invalidate the traditional loop design methodology which is based on analog loop design. We analyze the degradation in the OFDM schemes caused by the tracking loop and show how the performance is dependent on the rms phase error, where we distinguished between the effect of the variance in the average phase over the symbol and the effect of the phase change over the symbol. We derive the optimal tracking loop including optional delay in the loop caused by processing time. Our solution is general and includes arbitrary phase noise apd additive noise spectrums. In order to guarantee a well behaved solution, we have to check the design against margin constraints subject to uncertainties. In case the optimal loop does not meet the required margin constraints subjected to uncertainties, it is shown how to apply a method taken from control theory to find a controller. Alternatively, if we restrict the solution to first or second order loops, we give a simple loop design procedure which may be sufficient in many cases. Extensions of the method are shown for using both pilot symbols and data symbols in the OFDM receiver for phase tracking. We compare our results to other methods commonly used in OFDM receivers and we show that a large improvement can be gained.

• Journal of the Institute of Electronics Engineers of Korea TE
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• v.39 no.4
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• pp.403-408
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• 2002

In this paper, the performance on the PN code acquisition of DS/CDMA system was analyzed using the Nakagami-m probability density function considered fading environment. The equations on detection probability, $P_D$ and false alarm probability, ($P_{FA}$, decision variables affecting the PN code acquisition time were derived and proved using simulation in order to analyze the performance. In conclusion, It was necessary increasing the gain of PLL for correcting phase errors and improving the acquisition performance of PN code in apply to the rake receiver.

• Journal of Institute of Control, Robotics and Systems
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• v.14 no.9
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• pp.939-947
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• 2008

The GPS tracking loop consists of three parts in general: discriminator, loop filter and DCO (Digitally Controlled Oscillator). The loop filter is the main part of the tracking loop designed to ensure a good tracking performance. Generally, the loop filter is designed using classical PI(Proportional Integral) control. Although the carrier Doppler and code Doppler are generated by the same relative movement between the satellite and the user, often, the loop filters for each tracking loop are designed separately and independently. Sometimes, they are used in a combined manner such as carrier aided code tracking, FLL assisted PLL, etc. For better GPS signal tracking, we need to design the FLL/PLL/DLL altogether optimally. The purpose of this paper is to design a GPS receiver tracking loop based on the Kalman filter in a combined manner. Also, the proposed GPS receiver tracking loop is compared with a conventional tracking loop in terms of the transfer function and the DCO input. This paper shows that conventional tracking loop is equal to the Kalman filter based tracking loop.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.64 no.7
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• pp.1005-1011
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• 2015

This paper proposes the DC offset compensation algorithm with fast response to the sensed grid voltage in the single-phase grid connected inverter. If the sensor of the grid voltage has problems, the DC offset of the grid voltage can be generated. This error must be resolved because the DC offset can generate the estimated grid frequency error of the phase-locked loop (PLL). In conventional algorithm to compensate the DC offset, the DC offset is estimated by integrating the synchronous reference frame d-axis voltage during one period of the grid voltage. The conventional algorithm has a drawback that is a slow dynamic response because monitoring the one period of the grid voltage is required. the proposed algorithm has fast dynamic response because the DC offset is consecutively estimated by transforming the d-axis voltage to synchronous reference frame without monitoring one cycle time of the grid voltage. The proposed algorithm is verified from PSIM simulation and the experiment.

• Journal of Advanced Navigation Technology
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• v.2 no.1
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• pp.22-33
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• 1998

In the coherent-on-receiver radar system using the magnetron source, frequency synthesizer is employed as a STALO(Stable Local Oscillator) to keep the intermediate frequency stable. In this paper, X-band(8.4GHz~9.7GHz) single loop frequency synthesizer is designed and implemented by an indirect frequency synthesis technique. Phase comparison is performed by a digital PLL(Phase-Locked Loop) chip and the loop filter is designed for the low phase noise. The effects of loop component characteristics on the output phase noise are analyzed for single loop structures, and the calculated results are compared with the measured data.

• Journal of Power Electronics
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• v.16 no.2
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• pp.704-716
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• 2016

Small distributed generation units are usually connected to the main electric grid through single-phase voltage source inverters. Grid operating conditions such as voltage and frequency are not constant and can fluctuate within the range values established by international standards. Furthermore, the requirements in terms of power factor correction, total harmonic distortion, and reliability are getting tighter day by day. As a result, the implementation of reliable and efficient control algorithms, which are able to adjust their control parameters in response to changeable grid operating conditions, is essential. This paper investigates the configuration topology and control algorithm of a single-phase inverter with the purpose of achieving high performance in terms of efficiency as well as total harmonic distortion of the output current. Accordingly, a Second Order Generalized Integrator with a suitable Phase Locked Loop (SOGI-PLL) is the basis of the proposed current and voltage regulation. Some practical issues related to the control algorithm are addressed, and a solution for the control architecture is proposed, based on resonant controllers that are continuously tuned on the basis of the actual grid frequency. Further, intentional islanding operation is investigated and a possible procedure for switching from grid-tied to islanding operation and vice-versa is proposed.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.13 no.4
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• pp.285-301
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• 1988

The symbol error rate equations of multi-level quadrature PRS(QPRS) system have been derived in the individual and composite environment of Gaussian/impulsive noise, cochannel CW interference, carrier offset, phase jitter and fading. And using the derived error rate equations, the probability of error has been evaluated and shown in graphs as functions of carrier to noise power ratio, carrier to interference power ratio, phase error, impulsive index, the ration of Gaussian noise to impulsive noise power component, signal to noise power ration in phase locked loop(PLL), and fading figures. The rseults show that the error rate performances are generally more more degraded by impulsive noise than by Gaussian noise. But on the contrary the erors occurred more frequently by Gaussian noise than impulsive noise in a fading environment.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.28 no.11C
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• pp.1152-1160
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• 2003

Start The current paper proposes an improved HD(High Definition) monitor that can support a signal input with various resolutions. Due to the inadequate performance of the built-in digital PLL(Phase-locked Loop) of an ADC(Analog to Digital Converter) and poor tolerance of ADC ICs, there are problems in the stable processing of synchronization signals with various input signals. Accordingly, the proposed synchronization signal optimization technique regenerates the horizontal synchronization signal in the vertical blanking interval based on the regularity of the synchronization signal, i.e. the timing of the falling edge signal remains constant, thereby solving the above problem and minimizing the interference of the system. As a result, the proposed system can stabilize various synchronization signals with different resolution modes.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.25 no.1A
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• pp.27-33
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• 2000

Gardner’s algorithm is one of the useful algorithm for NDD(Non-Decision Directed) symbol synchronization in PAM communications. But the algorithm has a weak point such as pattern noises increasing in multi-level PAM. To insert a pre-filter in the algorithm is able to reduce timing jitter and pattern noise. In this paper, we analyze statistical properties of NDD algorithm to find an optimal parameter of the pre-filter for improving timing jitter and PLL locking. As a simulation result, optimum value of pre-filter parameter, $\beta$, is 0.3 and 0.5 at the roll off factor of the channel, $\alpha$, is 0.5 and 1.0, respectively. Optimum parameters of the pre-filter for clock synchronization of all-digital 256-QAM demodulator is shown in the results.