• The Bulletin of The Korean Astronomical Society
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• v.30 no.2
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• pp.29.1-29.1
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• 2005

• The Bulletin of The Korean Astronomical Society
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• v.26 no.2
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• pp.24.2-24.2
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• 2001

• 한국ITS학회:학술대회논문집
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• 2004.11a
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• pp.236-240
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• 2004

• Journal of the Institute of Convergence Signal Processing
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• v.6 no.2
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• pp.95-99
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• 2005

This paper presents an accurate recovery method of the reference clock which is needed for network synchronization in two-way satellite multimedia systems compliant with DVB-RCS specification and which use closed loop method for burst synchronization. In these systems, the remote station transmits TDMA burst via return link. For burst synchronization, it obtains reference clock from program clock reference (PCR) defined by MPEG-2 system specification. The PCR is generated periodically at the hub system by sampling system clock which runs at 27MHz $\pm$ 30ppm. Since the reference clock is recovered by means of digital PLL(DPLL) using imprecise PCR values due to variable random jitter, the recovered clock frequency of remote station doesn't exactly match reference clock of hub station. We propose a robust recovery method of reference clock against random delay jitter The simulation results show that the recovery error is remarkably decreased from 5 clocks to 1 clock of 27MHz relative to the general DPLL recovery method.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.17 no.2 s.105
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• pp.171-177
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• 2006

A low-cost, high-performance 40 Gb/s clock recovery module using a phase-locked loop(PLL) for a 40 Gb/s optical receiver with the clock-hold function has been designed and implemented. It consists of a clock extractor circuit, an RF mixer and a frequency discriminator for phase/frequency detection, a VC-DRO, a phase shifter, and a clock-hold circuit. The extracted 40 GHz clock is synchronized with a stable 10 GHz VC-DRO. The clock stability and jitter characteristics of the implemented PLL-based clock recovery module are significantly improved as compared with those of the conventional open-loop type clock recovery module with a DR filter. The measured peak-to-peak RMS jitter is about 230 fs. When an input signal is dropped, the 40 GHz clock is maintained continuously by the hold circuit.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.20 no.1
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• pp.48-56
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• 2006

This paper studies particularly applicable method for sensorless PM BLDC motor drive system. The waveform of the motor internal voltages(or back emf) contains a fundamental and higher order frequency harmonics. Therefore the third harmonic component is extracted from the stator phase voltage. The resulting third harmonic signal keeps a constant phase relationship with the rotor flux for any motor speed and load condition. Also because of low resolution of estimated signal obtained by the proposed sensorless algorithm, to improve the wide range of speed response characteristic more exactly, we propose the rotor position signal synthesizer using PLL circuit based on estimated signals. Some experimental results are provided to demonstrate the validity of the proposed control method.

• Journal of Astronomy and Space Sciences
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• v.20 no.3
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• pp.185-196
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• 2003

In this paper, we make a design study for a local oscillator system of the 100 ㎓ band cosmic radio receiving system. We use the YIG oscillator with digital driver which is the main oscillator. This oscillator has a good frequency and phase stability at some temperature variation, and the easy computer aided control characteristics. This total system designed to two subsystem, first is the oscillator system include YIG oscillator, tripler, harmonic mixer and triplexer etc., second is the PLL system to supply the precise and stable local oscillator frequency to mixer. The proposed local oscillator system in this paper can be used in a single or multi pixel receiver because this system can be lock the local oscillator frequency automatically using PC.

• Bulletin of the Korean Chemical Society
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• v.34 no.12
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• pp.3665-3670
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• 2013

The R3V6 peptide includes a hydrophilic arginine stretch and a hydrophobic valine stretch. In previous studies, the R3V6 peptide was evaluated as a gene carrier and was found to have low cytotoxicity. However, the transfection efficiency of R3V6 was lower than that of poly-L-lysine (PLL) in N2A neuroblastoma cells. In this study, the transfection efficiency of R3V6 was improved in combination with high mobility group box 1A domain (HMGA). HMGA is originated from the nuclear protein and has many positively-charged amino acids. Therefore, HMGA binds to DNA via charge interaction. In addition, HMGA has a nuclear localization signal peptide and may increase the delivery efficiency of DNA into the nucleus. The ternary complex with HMGA, R3V6, and DNA was prepared and evaluated as a gene carrier. First, the HMGA/DNA complex was prepared with a negative surface charge. Then, R3V6 was added to the complex to coat the negative charges of the HMGA/DNA complex, forming the ternary complex of HMGA, R3V6, and DNA. A physical characterization study showed that the ternary complex was more stable than the PLL/DNA complex. The HMGA/R3V6/DNA complex had a higher transfection efficiency than the PLL/DNA, HMGA/DNA, or R3V6/DNA complexes in N2A cells. Furthermore, the HMGA/R3V6/DNA complex was not toxic to cells. Therefore, the HMGA/R3V6/DNA complex may be a useful gene delivery carrier.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.20 no.9
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• pp.967-973
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• 2009

In this paper, X-band satellite communication oscillator of double phase locked is implemented by constructing a couple of phased-locked loop, and then we have analyzed the phase noise of designed PLL-DRO. The designed phase-locked oscillator is consist of series feedback DRO, frequency divider, phase detector, loop filter and programmable PLL-IC. By dividing oscillation frequency of 12.6 GHz into two frequencies, it exhibits output power of 15.32 dBm at 6.3 GHz. Phase noises of implemented oscillator are -81 dBc/Hz@100Hz, -100.86 dBc/Hz@1 kHz, -111.12 dBc/Hz@10 kHz, -116 dBc/Hz@100 kHz and -140.49 dBc/Hz@1 MHz respectively. These indicate excellent stable operation of oscillator and very good phase noise characteristics.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.4
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• pp.37-44
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• 2009

A novel phase-locked loop(PLL) architecture with resistance and capacitance scaling scheme has been proposed. The proposed PLL has three charge pumps. The effective capacitance and resistance of the loop filter can be scaled up/down according to the locking status by controlling the direction and magnitude of each charge pump current. This architecture makes it possible to have a narrow bandwidth and low resistance in the loop filter, which improves phase noise and reference spur characteristics. It has been fabricated with a 3.3V $0.35{\mu}m$ CMOS process. The measured locking time is $25{\mu}s$ with the measured phase noise of -105.37 dBc/Hz @1MHz and the reference spur of -50dBc at 851.2MHz output frequency