• Proceedings of the KIPE Conference
• /
• 2011.07a
• /
• pp.380-381
• /
• 2011

본 논문에서는 PFC 부스트 컨버터의 역률 및 고조파 왜율 개선을 위한 전류 제어기 이득 조정 기법을 제안한다. PFC단은 입력 전압의 변화에 따라 인덕터 전류의 크기가 달라져 부스트 인덕터의 인덕턴스가 변화하게 되어 전류 루프의 주파수 특성이 변화하게 된다. 이러한 현상으로 인한 전류 루프의 이득 변화를 분석하였다. 이를 기반으로 입력 전압에 따라 전류 제어기의 이득을 조정해 줌으로써, 충분한 위상마진을 확보함과 동시에 PF와 THD 성능을 개선한다. TI사의 TMS320F28027 MCU를 이용한 실험을 통해 제안된 기법의 유용성을 검증한다.

• Journal of Power Electronics
• /
• v.18 no.2
• /
• pp.323-331
• /
• 2018

Buck power factor correction (PFC) converters, compared with conventional boost PFC converters, exhibit high efficiency performance in the entire range of universal line voltage. This feature has gotten more attention for eliminating the zero crossing dead angle of buck PFC rectifiers. Furthermore, bridgeless structures for the reduction of conduction losses have been proposed. The aim of this paper is to introduce a single-phase buck rectifier that simultaneously has unity power factor (PF) and bridgeless structure while operating in the continuous conduction mode (CCM). For this purpose, two auxiliary flyback converters without any active switches are applied to a bridgeless buck rectifier to eliminate the zero crossing dead angle and achieve unity power factor, low total harmonic distortion (THD) and high efficiency. The operation and design considerations of the proposed rectifier are verified on a 150W, 48V prototype using a conventional peak-current-mode control. The measurement results show that the proposed rectifier has nearly unity power factor, THD less than 7% and high efficiency.

• Proceedings of the KIPE Conference
• /
• 2018.07a
• /
• pp.204-206
• /
• 2018

본 논문에서는 대용량 전력 어플리케이션에 적합한 인터리브드 토템폴 브리지리스 부스트 PFC 컨버터의 전입력전압 범위, 전부하에서 소프트 스위칭을 달성하여 높은 효율을 얻는 새로운 PFC 컨버터를 제안한다. 기존의 회로는 하드 스위칭에 의해 큰 스위칭 손실을 가져 효율이 낮을 뿐만 아니라 소자에 부담을 주어 높은 성능의 방열 시스템을 필요로 한다. 제안하는 컨버터는 하나의 인덕터가 추가되었으며, 위상 천이 기법을 통해 적절한 크기의 전류를 생성하여 소프트 스위칭을 달성하면서도 추가적인 손실을 최소화 한다. 따라서 전 부하에 걸쳐 높은 효율을 얻을 수 있다.

• Proceedings of the KIPE Conference
• /
• 2017.07a
• /
• pp.78-79
• /
• 2017

본 논문에서는 스위칭 손실을 저감한 고주파 인터리브드 토템폴 브리지리스 부스트 PFC 컨버터를 제안한다. 인터리브드 토템폴 브리지리스 부스트 PFC 컨버터는 하드 스위칭 동작을 하기 때문에 큰 스위칭 손실을 가지며, 고주파에서의 동작이 제한된다. 제안하는 컨버터는 수동 소자인 인덕터가 추가된 구조이며, 추가 인덕터의 에너지를 이용해 영전압 스위칭을 할 수 있다. 그 결과, 스위칭 손실이 저감되고 고주파 동작이 가능해진다. 또한 기존에 설계된 회로와 제어단을 그대로 유지할 수 있다.

• Proceedings of the KIEE Conference
• /
• 2009.04b
• /
• pp.152-155
• /
• 2009

In high power application, PFC(Power Factor Correction) pre-regulators are generally required. PFC pre-regulators could achieve unity power factor, reduce line input current harmonics and utilize full line power. Interleaving PFC converters could reduce input ripple current, output capacitor ripple current and inductor size. With this closed loop interleaving method, both two phase converters are working at the boundary between continuous and discontinuous mode and accurate 180 degree phase shift is achieved. Implementation of this strategy could be easily integrated to the control chip. Finally, experimental results of a two-phase interleaved boost PFC are presented to verify the discussed features.

• Proceedings of the KIPE Conference
• /
• 2001.07a
• /
• pp.219-222
• /
• 2001

In this paper, we firstly proposed to the boost type PFC circuit for a power factor improving and a harmonic decreasing. The predict current control method is used to control these PFC circuit. This current control method has a merit that is possible to improve power factor and harmonics. In addition, we suggested to the active DC filter, which is connected with the DC output terminal, in order to compensate the DC ripple components. Consequently, these results are proved by the simulation tool, PSIM, which is an exclusive simulator of power electronics.

• Proceedings of the KIPE Conference
• /
• 2014.07a
• /
• pp.181-182
• /
• 2014

본 논문에서는 동기 정류 스위치를 사용한 임계 도통 모드 부스트 PFC 컨버터의 디지털 제어 기법을 제안한다. 상태 궤적 분석을 통해 입력전압 전 범위의 영전압 스위칭 조건을 구하였으며, 총 입력 전하 분석을 통하여 높은 역률을 위한 스위치 추가 온-타임을 도출하였다. 제안하는 제어 기법은 디지털 제어기를 이용한 $230V_{rms}$ 입력, 400V/200W 출력 프로토타입에서 타당성을 입증하였다. 그 결과 동기 정류기를 이용한 임계 도통 모드 부스트 PFC 컨버터는 높은 역률 및 효율을 갖는다.

• Proceedings of the KIEE Conference
• /
• 1999.07f
• /
• pp.2562-2564
• /
• 1999

We have development the electronic ballast for metal halide discharge (MHD) lamp. The ballast consists of the boost pre-converter for power factor correction (PFC), a flyback a converter, half-bridge inverter and ignitor. To reject acoustic resonance phenomena, we have designed electronic ballast driving with the low frequency square wave. As results of this study, the ballast had not flicker phenomena and promoted corrected the factor (PF) highly

• The Transactions of the Korean Institute of Power Electronics
• /
• v.9 no.4
• /
• pp.390-396
• /
• 2004

Recently, there have been Increasing demands for high power factor and low harmonic distortion in the current drawn from utility. The harmonic limits imposed by international standards. It need the PFC techniques in order to reduce line current harmonics and comply with the standards. The average current control method that is the most proper PFC control method in a switching power supply of middle and high power has been used mostly to PFC control method. However, the switching device of PFC circuit has frequently destructed at power return after instantaneous power interrupt. Therefore, this paper have verified the cause of this problems and proposed the solution through simulation and experiment

• Journal of Power Electronics
• /
• v.12 no.1
• /
• pp.104-112
• /
• 2012

In this paper a new method for the design of a simple PI controller is presented and it has been applied in the control of a Boost based PFC rectifier. The Strength Pareto evolutionary algorithm, which is based on the Pareto Optimality concept, used in Game theory literature is implemented as a multi-objective optimization approach to gain a good transient response and a high quality input current. In the proposed method, the input current harmonics and the dynamic response have been assumed as objective functions, while the PI controller's gains of the PFC rectifier (Kpi, Tpi) are design variables. The proposed algorithm generates a set of optimal gains called a Pareto Set corresponding to a Pareto Front, which is a set of optimal results for the objective functions. All of the Pareto Front points are optimum, but according to the design priority objective function, each one can be selected. Simulation and experimental results are presented to prove the superiority of the proposed design methodology over other methods.