• JSTS:Journal of Semiconductor Technology and Science
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• v.11 no.3
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• pp.162-168
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• 2011

In this paper, we propose a new Verilog-A current-voltage model for multi-level-cell PCRAMs. This model can describe the PCRAM operation not only in full SET and RESET states but also in the partial resistance states. And, 3 PCRAM operating regions of SET-RESET, Negative Differential Resistance, and strong-ON are unified into one equation in this model thereby any discontinuity that may introduce a convergence problem cannot be found in the new PCRAM model. The percentage error between the measured data and this model is as small as 7.4% on average compared to 60.1% of the previous piecewise model. The parameter extraction which is embedded in the Verilog-A code can be done automatically.

• JSTS:Journal of Semiconductor Technology and Science
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• v.13 no.1
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• pp.58-64
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• 2013

In this paper, two new flip-flop circuits with PCRAM latches that are FF-1 and FF-2, respectively, are proposed not to waste leakage during sleep time. Unlike the FF-1 circuit that has a normal PCRAM latch, the FF-2 circuit has a selective write latch that can reduce the switching activity in writing operation to save switching power at sleep-in moment. Moreover, a sequential sleep-in control is proposed to reduce the rush current peak that is observed at the sleep-in moment. From the simulation of storing '000000' to the PCRAM latch, we could verify that the proposed FF-1 and FF-2 consume smaller power than the conventional 45-nm FF if the sleep time is longer than $465{\mu}s$ and $95{\mu}s$, respectively, at $125^{\circ}C$. For the rush current peak, the sequential sleep-in control could reduce the current peak as much as 77%.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.27 no.2
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• pp.76-80
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• 2014

Dual-gate PCRAM which unify capacitor-less DRAM and NVM using a PCM instead of a typical SONOS flash memory is proposed as 1 transistor. $VO_2$ changes its phase between insulator and metal states by temperature and field. The front-gate and back-gate control NVM and DRAM, respectively. The feasibility of URAM is investigated through simulation using c-interpreter and finite element analysis. Threshold voltage of NVM is 0.5 V that is based on measured results from previous fabricated 1TPCM with $VO_2$. Current sensing margin of DRAM is 3 ${\mu}A$. PCM does not interfere with DRAM in the memory characteristics unlike SONOS NVM. This novel unified dual-gate PCRAM reported in this work has 1 transistor, a low RESET/SET voltage, a fast write/erase time and a small cell so that it could be suitable for future production of URAM.

• Proceedings of the KIEE Conference
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• 2006.07c
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• pp.1438-1439
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• 2006

$Ge_{2}Sb_{2}Te_5$(GST) thin film at present is a promising candidate for a phase change random access memory (PCRAM) based on the difference in resistivity between the crystalline and amorphous phase. PCRAM is an easy to manufacture, low cost storage technology with a high storage density. Therefore today several major chip in manufacturers are investigating this data storage technique. Recently, A. Pirovano et al. showed that PCRAM can be safely scaled down to the 65 nm technology node. G. T Jeonget al. suggested that physical limit of PRAM scaling will be around 10 nm node. Etching process of GST thin ra films below 100 nm range becomes more challenging. However, not much information is available in this area. In this work, we report on a parametric study of ICP etching of GST thin films in $Cl_2$/Ar chemistry. The etching characteristics of $Ge_{2}Sb_{2}Te_5$ thin films were investigated using an inductively coupled plasma (ICP) of $Cl_2$/Ar gas mixture. The etch rate of the GST films increased with increasing $Cl_2$ flow rate, source and bias powers, and pressure. The selectivity of GST over the $SiO_2$ films was higher than 10:1. X-ray photoelectron spectroscopy(XPS) was performed to examine the chemical species present in the etched surface of GST thin films. XPS results showed that the etch rate-determining element among the Ge, Sb, and Te was Te in the $Cl_2$/Ar plasma.

• Proceedings of the Korean Vacuum Society Conference
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• 2011.02a
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• pp.55-55
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• 2011

질소 등을 GST225 상변화재료에 첨가시켜 비저항을 증가시킴으로서 PCRAM의 동작 전류를 감소시킨 연구가 선행된 바 있다. 본 연구에서는 GST225와 달리 고속 동작 특성을 갖는 것으로 널리 알려진 Ge-doped SbTe (GeST) 상변화 재료에 Carbon을 첨가하여 박막 특성을 연구하여 동작 전류 감소의 가능성을 타진하였다. 실험을 위한 박막 제작을 위해 2 inch size의 GeST 및 C doped GeST (C-GeST) single target을 이용하여 RF magnetron co-sputtering 하였다. 박막은 carbon이 첨가되지 않은 GeST와 carbon 첨가량이 늘어나는 순서로 C-GeST 1, C-GeST 2, C-GeST 3로 구성된다. 이 때 제작한 박막의 composition analysis를 위해 XRF/RBS/AES가 사용되었고 제작된 박막의 기본적인 특성평가를 위해 resistivity(${\rho}$)와 crystallzation temp.(Cx), surface morphology(AFM), x-ray diffraction pattern(XRD)를 측정하였다. 실험결과 GeST, C-GeST 1, C-GeST 2, C-GeST 3 박막의 Cx는 각각 209, 225, 233, $245^{\circ}C$로 측정되어 carbon 첨가량이 증가됨에 따라 결정화 온도가 증가되는 것을 알 수 있었다. 또한 ${\rho}$도 마찬가지로 annealing 온도를 약 $320^{\circ}C$로 할 경우 ${\rho}$(as-dep)와 ${\rho}$(crystalline) 모두 0.03 / $2.61*10^{-6}$, 0.08 / $7.93*10^{-6}$, 0.09 / $11.99*10^{-6}$, 0.13 / $13.49*10^{-6}{\Omega}{\cdot}m$로 증가하였다. 증가된 ${\rho}$의 원인이 박막의 grain size의 감소라고 단언 할 수는 없으나 AFM 측정결과 grain이라고 추측되는 박막 feature들의 size가 점차 감소하는 것을 확인하였다.

• Proceedings of the Korean Vacuum Society Conference
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• 2013.02a
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• pp.250-250
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• 2013

본 연구에서는 차세대 상변화메모리(PCRAM)와 초고속 소자(FET) 등의 응용을 위하여 사용되고 있는 Ge 소재를 제조하기 위해새롭게 전구체를 개발하고 이를 CVD (Chemical Vapor Deposition) 공정을 이용하여 증착실험을 실시하였다. 새롭게 개발된 Ge 전구체 (isopropyl germane)는 기존 Ge 전구체보다 합성비용이 경제적이며 공정이 간단하고 상업적 생산에도 적합하다는 장점을 갖고 있다. Ge 박막의 증착은 증착압력, 증착온도, reactive gas (H2) 유량, carrier gas(Ar) 유량, 기판(Si, Pt 등) 등을 변수로 하여 실험하였다. 증착된 박막에 대하여 FE-SEM, XRD 등을 통하여 기본적인 물성분석을 실시하였다.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.25 no.5
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• pp.329-333
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• 2012

For phase transition method, good record sensitivity, low heat radiation, fast crystallization and hi-resolution are essential. Also, a retention time is very important part for phase-transition. In our past papers, we chose composition of $Ge_1Se_1Te_2$ material to use a Se factor which has good optical sensitivity than conventional Sb. Sb/Ge-Se-Te thin films are fabricated and irradiated with UV light source to investigate a reversible phase change by Sb-doped condition. Because of Sb atoms, the Sb inserted sample showed better performance than conventional one. We should note that this novel one showed another possibility for phase-change random access memory.