• Title/Summary/Keyword: PA(Power Amplifier)

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A Highly Linear and Efficient DMB CMOS Power Amplifier with Adaptive Bias Control and 2nd Harmonic Termination circuit (적응형 바이어스 조절 회로와 2차 고조파 종단 회로를 이용한 고선형성 고효율 DMB CMOS 전력증폭기)

  • Choi, Jae-Won;Seo, Chul-Hun
    • Journal of the Institute of Electronics Engineers of Korea TC
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    • v.44 no.1
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    • pp.32-37
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    • 2007
  • A DMB CMOS power amplifier (PA) with high efficiency and linearity is present. For this work, a 0.13-um standard CMOS process is employed and all components of the proposed PA are fully integrated into one chop including output matching network and adaptive bias control circuit. To improve the efficiency and linearity simultaneously, an adaptive bias control circuit is adopted along with second harmonic termination circuit at the drain node. The PA is shown a $P_{1dB}$ of 16.64 dBm, power added efficiency (PAE) of 38.31 %, and power gain of 24.64 dB, respectively. The third-order intermodulation (IMD3) and the fifth-order intermodulation (IMD5) have been -24.122 dBc and -37.156 dBc, respectively.

6-18 GHz Reactive Matched GaN MMIC Power Amplifiers with Distributed L-C Load Matching

  • Kim, Jihoon;Choi, Kwangseok;Lee, Sangho;Park, Hongjong;Kwon, Youngwoo
    • Journal of electromagnetic engineering and science
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    • v.16 no.1
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    • pp.44-51
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    • 2016
  • A commercial $0.25{\mu}m$ GaN process is used to implement 6-18 GHz wideband power amplifier (PA) monolithic microwave integrated circuits (MMICs). GaN HEMTs are advantageous for enhancing RF power due to high breakdown voltages. However, the large-signal models provided by the foundry service cannot guarantee model accuracy up to frequencies close to their maximum oscillation frequency ($F_{max}$). Generally, the optimum output load point of a PA varies severely according to frequency, which creates difficulties in generating watt-level output power through the octave bandwidth. This study overcomes these issues by the development of in-house large-signal models that include a thermal model and by applying distributed L-C output load matching to reactive matched amplifiers. The proposed GaN PAs have successfully accomplished output power over 5 W through the octave bandwidth.

A Highly Linear and Efficiency Class-F Power Amplifier using PBG and application EER Structure (EER 구조의 응용과 PBG를 이용한 고효율, 고선형성 Class-F 전력 증폭기)

  • Lee, Chong-Min;Seo, Chul-Hun
    • Journal of the Institute of Electronics Engineers of Korea TC
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    • v.44 no.2
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    • pp.81-86
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    • 2007
  • In this paper, the Power Added Efficiency (PAE) and linearity of class-F PA has been improved by using the PBG structure and the application of EER structure, simultaneously. The adaptive bias control circuit has been employed to improve the PAE through the application of EER structure. The PBG structure has been adapted for improving the Linearity by suppressing the harmonics on the output of amplifier. The PAE and the 3rd Inter-Modulation Distortion (IMD) has improved 34.56%, 10.66 dB, compared with those of the conventional Doherty amplifier, respectively.

Development of a Side Scan Sonar System for Underwater Sun (천해용 Side Scan Sonar의 송수신 시스템 구현 및 운용에 관한 연구)

  • 오영석;이철원;강도욱;우종식
    • Proceedings of the Korea Committee for Ocean Resources and Engineering Conference
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    • 2000.10a
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    • pp.222-227
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    • 2000
  • "Side scan sonar" using acoustic signal has been developed to survey cable laying, sunken bodie\ulcorner bottom and so on. It use the acoustic signals, which are emitted from two transducer arrays, to get gemetri\ulcorner target area. This system consists of transceiver board, towed body, and deck unit. The transceiver board, w\ulcorner watertight canister of the towed body, controls the transmitting and receiving of 400kHz acoustic signals from \ulcorner After receiving the scattered signals, it processes the filtering, AGF(Automatic Gain Control), TVG(Time Heterodyne. The deck unit is composed of the signal processing part, A/D converter, power supplier, and real\ulcorner And the towed body has been designed to satisfy the optimal hydrodynamic behavior during towing. The de\ulcorner theory of transceiving part and some results from field-experiments will be introduced here.

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A CMOS Band-Pass Delta Sigma Modulator and Power Amplifier for Class-S Amplifier Applications (S급 전력 증폭기 응용을 위한 CMOS 대역 통과델타 시그마 변조기 및 전력증폭기)

  • Lee, Yong-Hwan;Kim, Min-Woo;Kim, Chang-Woo
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.40 no.1
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    • pp.9-15
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    • 2015
  • A CMOS band-pass delta-sigma modulator(BPDSM) and cascode class-E power amplifier have been developed CMOS for Class-S power amplifier applications. The BPDSM is operating at 1-GHz sampling frequency, which converts a 250-MHz sinusoidal signal to a pulse-width modulated digital signal without the quantization noise. The BPDSM shows a 25-dB SQNR(Signal to Quantization Noise Ratio) and consumes a power of 24 mW at an 1.2-V supply voltage. The class-E power amplifier exhibits an 18.1 dBm of the maximum output power with a 25% drain efficiency at a 3.3-V supply voltage. The BPDSM and class-E PA were fabricated in the Dongbu's 110-nm CMOS process.

A Study on Reduction of Mutual Nonlinear Interferences in Cognitive Radio System (무선 인지형 시스템에서 상호 비선형 간섭 감소에 관한 연구)

  • Lee, Yun-Min;Shin, Jin-Seob
    • The Journal of the Institute of Internet, Broadcasting and Communication
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    • v.18 no.5
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    • pp.283-288
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    • 2018
  • In this paper, it is required that the next generation wireless transmission system can support a large number of users without distortion of transmission signal with high data rate in various different propagation environment while using limited resources as efficiently as possible, and therefore an efficient transmission system is continuously required. Because of the large amount of data to be handled in a limited frequency band, a very complex digital modulation scheme is adopted. the linearity of the power amplifier determines the linearity of the entire communication system, and thus a linear amplifier is required. In cognitive radion systems, there is a power control issue in the relationship between primary and secondary users. This problem is solved by simulating the communication system so as to select the cognitive radio power while power control while overcoming linearity by using feed-forward PA.

Design of a Dual Band High PAE Power Amplifier using Single FET and Class-F (Single FET와 Class-F급을 이용한 이중대역 고효율 전력증폭기 설계)

  • Kim, Seon-Sook;Seo, Chul-Hun
    • Journal of the Institute of Electronics Engineers of Korea TC
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    • v.45 no.1
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    • pp.110-114
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    • 2008
  • In this paper, high efficient class F power amplifier with dual band has been realized. Dual band power amplifier have used modify stub matching for single FET, center frequency 2.14GHz and 5.2GHz respectively. Dual band amplifier is 32.65dBm output power, gain 11dB and PAE 36% at the 2.14GHz, 7dB gain at the 5.2GHz. Design of a dual band class F power amplifier using harmonic control circuit. The measured are 9.9dB gain, 30dBm output power and PAE 55% at the 2.14GHz, 11.7dB gain at the 5.2GHz. This paper is being used the load-pull method and it maximizes output power and it is using the only one transistor in the paper. As a result, this research will obtain a dual band high PAE power amplifier.

High-Efficiency CMOS Power Amplifier using Low-Loss PCB Balun with Second Harmonic Impedance Matching (2차 고조파 정합 네트워크를 포함하는 저손실 PCB 발룬을 이용한 고효율 CMOS 전력증폭기)

  • Kim, Hyungyu;Lim, Wonseob;Kang, Hyunuk;Lee, Wooseok;Oh, Sungjae;Oh, Hansik;Yang, Youngoo
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.30 no.2
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    • pp.104-110
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    • 2019
  • In this paper, a complementary metal oxide semiconductor(CMOS) power amplifier(PA) integrated circuit operating in the 900 MHz band for long-term evolution(LTE) communication systems is presented. The output matching network based on a transformer was implemented on a printed circuit board for low loss. Simultaneously, to achieve high efficiency of the PA, the second harmonic impedances are controlled. The CMOS PA was fabricated using a $0.18{\mu}m$ CMOS process and measured using an LTE uplink signal with a bandwidth of 10 MHz and peak to average power ratio of 7.2 dB for verification. The implemented CMOS PA module exhibits a power gain of 24.4 dB, power-added efficiency of 34.2%, and an adjacent channel leakage ratio of -30.1 dBc at an average output power level of 24.3 dBm.

A 2.4-GHz Dual-Mode CMOS Power Amplifier with a Bypass Structure Using Three-Port Transformer to Improve Efficiency (3-포드 변압기를 이용한 바이패스 구조를 적용하여 효율이 개선된 이중 모드 2.4-GHz CMOS 전력 증폭기)

  • Jang, Joseph;Yoo, Jinho;Lee, Milim;Park, Changkun
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.23 no.6
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    • pp.719-725
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    • 2019
  • We propose a 2.4-GHz CMOS power amplifier (PA) with a bypass structure to improve the power-added efficiency (PAE) in the low-power region. The primary winding of the output transformer is split into two parts. One of the primary windings is connected to the output of the power stage for high-power mode. The other primary winding is connected to the output of the driver stage for low-power mode. Operation of the high power mode is similar to conventional PAs. On the other hand, the output power of the driver stage becomes the output power of the overall PA in the low power mode. Owing to a turning-off of the power stage, the power consumption is decreased in low-power mode. We designed the CMOS PA using a 180-nm RFCMOS process. The measured maximum output power is 27.78 dBm with a PAE of 20.5%. At a measured output power of 16 dBm, the PAE is improved from 2.5% to 12.7%.

Class-E CMOS PAs for GSM Applications

  • Lee, Hong-Tak;Lee, Yu-Mi;Park, Chang-Kun;Hong, Song-Cheol
    • Journal of electromagnetic engineering and science
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    • v.9 no.1
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    • pp.32-37
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    • 2009
  • Various Class-E CMOS power amplifiers for GSM applications are presented. A stage-convertible transformer for a dual mode power amplifier is proposed to increase efficiency in the low-output power region. An integrated passive device(IPD) process is used to reduce combiner losses. A split secondary 1:2 transformer with IPD process is designed to obtain efficient and symmetric power combining. A quasi-four-pair structure of CMOS PA is also proposed to overcome the complexities of power combining.