• Title/Summary/Keyword: PA(Power Amplifier)

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A Fully Integrated Dual-Band WLP CMOS Power Amplifier for 802.11n WLAN Applications

  • Baek, Seungjun;Ahn, Hyunjin;Ryu, Hyunsik;Nam, Ilku;An, Deokgi;Choi, Doo-Hyouk;Byun, Mun-Sub;Jeong, Minsu;Kim, Bo-Eun;Lee, Ockgoo
    • Journal of electromagnetic engineering and science
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    • v.17 no.1
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    • pp.20-28
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    • 2017
  • A fully integrated dual-band CMOS power amplifier (PA) is developed for 802.11n WLAN applications using wafer-level package (WLP) technology. This paper presents a detailed design for the optimal impedance of dual-band PA (2 GHz/5 GHz PA) output transformers with low loss, which is provided by using 2:2 and 2:1 output transformers for the 2 GHz PA and the 5 GHz PA, respectively. In addition, several design issues in the dual-band PA design using WLP technology are addressed, and a design method is proposed. All considerations for the design of dual-band WLP PA are fully reflected in the design procedure. The 2 GHz WLP CMOS PA produces a saturated power of 26.3 dBm with a peak power-added efficiency (PAE) of 32.9%. The 5 GHz WLP CMOS PA produces a saturated power of 24.7 dBm with a PAE of 22.2%. The PA is tested using an 802.11n signal, which satisfies the stringent error vector magnitude (EVM) and mask requirements. It achieved an EVM of -28 dB at an output power of 19.5 dBm with a PAE of 13.1% at 2.45 GHz and an EVM of -28 dB at an output power of 18.1 dBm with a PAE of 8.9% at 5.8 GHz.

CMOS Linear Power Amplifier with Envelope Tracking Operation (Invited Paper)

  • Park, Byungjoon;Kim, Jooseung;Cho, Yunsung;Jin, Sangsu;Kang, Daehyun;Kim, Bumman
    • Journal of electromagnetic engineering and science
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    • v.14 no.1
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    • pp.1-8
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    • 2014
  • A differential-cascode CMOS power amplifier (PA) with a supply modulator for envelope tracking (ET) has been implemented by 0.18 ${\mu}m$ RF CMOS technology. The loss at the output is minimized by implementing the output transformer on a FR-4 printed circuit board (PCB). The CMOS PA utilizes the $2^{nd}$ harmonic short at the input to enhance the linearity. The measurement was done by the 10MHz bandwidth 16QAM 6.88 dB peak-to-average power ratio long-term evolution (LTE) signal at 1.85 GHz. The ET operation of the CMOS PA with the supply modulator enhances the power-added efficiency (PAE) by 2.5, to 10% over the stand-alone CMOS PA for the LTE signal. The ET PA achieves a PAE of 36.5% and an $ACLR_{E-UTRA}$ of -32.7 dBc at an average output power of 27 dBm.

Ultra-small Form-Factor Helix on Pad-Type Stage-Bypass WCDMA Tx Power Amplifier Using a Chip-Stacking Technique and a Multilayer Substrate

  • Yoo, Chang-Hyun;Kim, Jung-Hyun
    • ETRI Journal
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    • v.32 no.2
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    • pp.327-329
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    • 2010
  • A fully integrated small form-factor HBT power amplifier (PA) was developed for UMTS Tx applications. For practical use, the PA was implemented with a well configured bottom dimension, and a CMOS control IC was added to enable/disable the HBT PA. By using helix-on-pad integrated passive device output matching, a chip-stacking technique in the assembly of the CMOS IC, and embedding of the bulky inductive lines in a multilayer substrate, the module size was greatly reduced to 2 mm ${\times}$ 2.2 mm. A stage-bypass technique was used to enhance the efficiency of the PA. The PA showed a low idle current of about 20 mA and a PAE of about15% at an output power of 16 dBm, while showing good linearity over the entire operating power range.

Effects of Drain Bias on Memory-Compensated Analog Predistortion Power Amplifier for WCDMA Repeater Applications

  • Lee, Yong-Sub;Lee, Mun-Woo;Kam, Sang-Ho;Jeong, Yoon-Ha
    • Journal of electromagnetic engineering and science
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    • v.9 no.2
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    • pp.78-84
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    • 2009
  • This paper represents the effects of drain bias on the linearity and efficiency of an analog pre-distortion power amplifier(PA) for wideband code division multiple access(WCDMA) repeater applications. For verification, an analog predistorter(APD) with three-branch nonlinear paths for memory-effect compensation is implemented and a class-AB PA is fabricated using a 30-W Si LOMaS. From the measured results, at an average output power of 33 dBm(lO-dB back-off power), the PA with APD shows the adjacent channel leakage ratio(ACLR, ${\pm}$5 MHz offset) of below -45.1 dBc, with a drain efficiency of 24 % at the drain bias voltage($V_{DD}$) of 18 V. This compared an ACLR of -36.7 dEc and drain efficiency of 14.1 % at the $V_{DD}$ of 28 V for a PA without APD.

A Highly Efficient Multi-Mode Balanced Power Amplifier for W-CDMA Handset Applications (W-CDMA 단말기용 고효율 다중 모드 Balanced 전력증폭기)

  • Kim, Un-Ha;Park, Sung-Hwan;Park, Hong-Jong;Kwon, Young-Woo;Kim, Jung-Hyun
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.23 no.5
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    • pp.606-612
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    • 2012
  • A highly efficient multi-mode balanced power amplifier(PA) structure is proposed for W-CDMA handset applications. The proposed PA has 2-stage amplifier configuration and the stage-bypass and load impedance switching techniques were applied to enhance power efficiency at medium power level as well as low output power level. Using the two techniques, four highly efficient power modes were realized. To demonstrate the usefulness of the proposed structure, a GaAs HBT balanced PA module was designed, fabricated, and measured.

A Fully Integrated 5-GHz CMOS Power Amplifier for IEEE 802.11a WLAN Applications

  • Baek, Sang-Hyun;Park, Chang-Kun;Hong, Song-Cheol
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.7 no.2
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    • pp.98-101
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    • 2007
  • A fully integrated 5-GHz CMOS power amplifier for IEEE 802.11a WLAN applications is implemented using $0.18-{\mu}m$ CMOS technology. An on-chip transmission-line transformer is used for output matching network and voltage combining. Input balun, inter-stage matching components, output transmission line transformer and RF chokes are fully integrated in the designed amplifier so that no external components are required. The power amplifier occupies a total area of $1.7mm{\times}1.2mm$. At a 3.3-V supply voltage, the amplifier exhibits a 22.6-dBm output 1-dB compression point, 23.8-dBm saturated output power, 25-dB power gain. The measured power added efficiency (PAE) is 20.1 % at max. peak, 18.8% at P1dB. When 54 Mbps/64 QAM OFDM signal is applied, the PA delivers 12dBm of average power at the EVM of -25dB.

A High-Efficiency CMOS Power Amplifier Using 2:2 Output Transformer for 802.11n WLAN Applications

  • Lee, Ockgoo;Ryu, Hyunsik;Baek, Seungjun;Nam, Ilku;Jeong, Minsu;Kim, Bo-Eun
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.15 no.2
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    • pp.280-285
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    • 2015
  • A fully integrated high-efficiency linear CMOS power amplifier (PA) is developed for 802.11n WLAN applications using the 65-nm standard CMOS technology. The transformer topology is investigated to obtain a high-efficiency and high-linearity performance. By adopting a 2:2 output transformer, an optimum impedance is provided to the PA core. Besides, a LC harmonic control block is added to reduce the AM-to-AM/AM-to-PM distortions. The CMOS PA produces a saturated power of 26.1 dBm with a peak power-added efficiency (PAE) of 38.2%. The PA is tested using an 802.11n signal, and it satisfies the stringent error vector magnitude (EVM) and mask requirements. It achieves -28-dB EVM at an output power of 18.6 dBm with a PAE of 14.7%.

Look-up Table type Digital Pre-distorter for Linearization Power Amplifier with Non-linearity and Memory Effect (전력증폭기의 비선형 특성과 Memory Effect를 보상하기 위한 Look-up Table 방식의 Digital Pre-distorter)

  • Choi, Hong-Min;Kim, Wang-Rae;Lyu, Jae-Woo;Ahn, Kwang-Eun
    • 한국정보통신설비학회:학술대회논문집
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    • 2008.08a
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    • pp.218-222
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    • 2008
  • RF power amplifier requires linearization in order to reduce adjacent channel interference. And most of the existing linearization algorithms assume that a PA has memory-less nonlinearity. But for the wider bandwidth signal, the memory effect of PA cannot be ignored. This paper investigates digital pre-distortion by use of a memory polynomial model which compensates for amplifier nonlinearity and memory effect. The look-up table based implementation scheme is used to reduce the computational complexity of the pre-distortion block. The linearization performance is demonstrated on wideband CDMA signal and class AB high power amplifier.

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2.4-GHz Power Amplifier with Power Detector Using Metamaterial-Based Transformer-Type On-Chip Directional Coupler

  • Dang, Trung-Sinh;Tran, Anh-Dung;Lee, Bomson;Yoon, Sang-Woong
    • ETRI Journal
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    • v.35 no.3
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    • pp.554-557
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    • 2013
  • This letter presents a power amplifier (PA) with an on-chip power detector for 2.4-GHz wireless local area network application. The power detector consists of a clamp circuit, a diode detector, and a coupled line directional coupler. A series inductor for an output matching network in the PA is combined with a through line of the coupler, which reduces the coupling level. Therefore, the coupler employs a metamaterial-based transformer configuration to increase coupling. The amount of coupling is increased by 2.5 dB in the 1:1 symmetric transformer structure and by 4.5 dB from two metamaterial units along the coupled line.

Design of Current-Mode Class-D 900 MHz RF Power Amplifier Using Inverse Class-F Technology (Inverse Class-F 기법을 이용한 900 MHz 전류 모드 Class-D RF 전력 증폭기 설계)

  • Kim, Young-Woong;Lim, Jong-Gyun;Kang, Won-Shil;Ku, Hyun-Chul
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.22 no.12
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    • pp.1060-1068
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    • 2011
  • In this paper, Current-Mode Class-D(CMCD) RF Power Amplifier(PA) is designed and implemented at 900 MHz. Conventional CMCD PA has output parallel resonator to reconstruct a fundamental frequency component of the output signal. However the resonator can be removed by connecting inverse class-F PAs because even-harmonic components can be removed by CMCD PA's push-pull structure. Using load-pull, inverse class-F PA with GaN transistors is designed, and CMCD PA with the inverse class-F PA is implemented. The CMCD PA has 64.5 % drain efficiency, 34.2 dBm output power. Comparing with the drain efficiency of a CMCD PA with parallel resonator, the CMCD with the inverse class-F technology has 13.6 % improved drain efficiency.