• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.12 s.354
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• pp.65-73
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• 2006

This work presents a 14b 200KS/s $0.87mm^2$ 1.2mW 0.18um CMOS algorithmic A/D converter (ADC) for intelligent sensors control systems, battery-powered system applications simultaneously requiring high resolution, low power, and small area. The proposed algorithmic ADC not using a conventional sample-and-hold amplifier employs efficient switched-bias power-reduction techniques in analog circuits, a clock selective sampling-capacitor switching in the multiplying D/A converter, and ultra low-power on-chip current and voltage references to optimize sampling rate, resolution, power consumption, and chip area. The prototype ADC implemented in a 0.18um 1P6M CMOS process shows a measured DNL and INL of maximum 0.98LSB and 15.72LSB, respectively. The ADC demonstrates a maximum SNDR and SFDR of 54dB and 69dB, respectively, and a power consumption of 1.2mW at 200KS/s and 1.8V. The occupied active die area is $0.87mm^2$.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.4
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• pp.53-63
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• 2009

This work proposes a 10b 100MS/s 27.2mW $0.8mm^2$ 0.18um CMOS ADC for WLAN such as an IEEE 802.11n standard. The proposed ADC employs a three-stage pipeline architecture and minimizes power consumption and chip area by sharing as many circuits as possible. Two multiplying DACs share a single amplifier without MOS switches connected in series while the shared amplifier does not show a conventional memory effect. All three flash ADCs use only one resistor ladder while the second and third flash ADCs share all pre-amps to further reduce power consumption and chip area. The interpolation circuit employed in the flash ADCs halves the required number of pre-amps and an input-output isolated dynamic latch reduces the increased kickback noise caused by the pre-amp sharing. The prototype ADC implemented in a 0.18um n-well 1P6M CMOS process shows the DNL and INL within 0.83LSB and 1.52LSB at 10b, respectively. The ADC measures an SNDR of 52.1dB and an SFDR of 67.6dB at a sampling rate of 100MS/s. The ADC with an active die area of $0.8mm^2$ consumes 27.2mW at 1.8V and 100MS/s.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.3
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• pp.77-85
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• 2008

This work proposes a 12b 130MS/s 108mW $1.8mm^2$ 0.18um CMOS ADC for high-quality video systems such as TFT-LCD displays and digital TVs requiring simultaneously high resolution, low power, and small size at high speed. The proposed ADC optimizes power consumption and chip area at the target resolution and sampling rate based on a three-step pipeline architecture. The input SHA with gate-bootstrapped sampling switches and a properly controlled trans-conductance ratio of two amplifier stages achieves a high gain and phase margin for 12b input accuracy at the Nyquist frequency. A signal-insensitive 3D-fully symmetric layout reduces a capacitor and device mismatch of two MDACs. The proposed supply- and temperature- insensitive current and voltage references are implemented on chip with a small number of transistors. The prototype ADC in a 0.18um 1P6M CMOS technology demonstrates a measured DNL and INL within 0.69LSB and 2.12LSB, respectively. The ADC shows a maximum SNDR of 53dB and 51dB and a maximum SFDR of 68dB and 66dB at 120MS/s and 130MS/s, respectively. The ADC with an active die area of $1.8mm^2$ consumes 108mW at 130MS/s and 1.8V.

• 대한핵의학회:학술대회논문집
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• 2000.05a
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• pp.58.2-58.2
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• 2000

• Journal of the Institute of Electronics and Information Engineers
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• v.49 no.10
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• pp.159-168
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• 2012

In this paper, a W-band single-chip receiver MMIC for FMCW(Frequency-modulated continuous-wave) radar is presented using $0.15{\mu}m$ GaAs pHEMT technology. The receiver MMIC consists of a 4-stage low noise amplifier(LNA), a down-converting mixer and a 3-stage LO buffer amplifier. The LNA is designed to exhibit a low noise figure and high linearity. A resistive mixer is adopted as a down-converting mixer in order to obtain high linearity and low noise performance at low IF. An additional LO buffer amplifier is also demonstrated to reduce the required LO power of the W-band mixer. The fabricated W-band single-chip receiver MMIC shows an excellent performance such as a conversion gain of 6.2 dB, a noise figure of 5.0 dB and input 1-dB compression point($P_{1dB,in}$) of -12.8 dBm, at the RF frequency of $f_0$ GHz, LO input power of -1 dBm and IF frequency of 100 MHz.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.9
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• pp.15-22
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• 2000

The effects of carrier transport and input power on the extinction ratio was theoretically analyzed in a 1.55${\mu}m$ InGaAsP/InGaAsP multiple-quantum-well(MQW) electroabsorption(EA) modulator. Poisson's equation, current continuity equations for electrons and holes, and optical field distribution were self-consistently solved by considering electric field dependent absorption coefficients. The field screening effect due to the carrier accumulation in heterointerface and the space-charge region occurred more seriously at the input side of modulator as input optical intensity increased. It was revealed that extinction ratio could be steeply degraded for modulator with the length of 200${\mu}m$ when an input power exceeds 10mW. A degradation of extinction ratio due to the field screening effect would be more significantly at high-performance devices such as a 1.55${\mu}m$DFB-LD/EA-modulator integrated source where optical coupling efficiency is almost complete or a very high-speed modulator with its length as short as a few tens ${\mu}m$.

• Korean Journal of Soil Science and Fertilizer
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• v.47 no.6
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• pp.533-539
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• 2014

Mine wastes such as acid mine drainage (AMD) can cause the detrimental effects on surrounding environment, thereby eventually threatening human health. Main objective of this study was to evaluate the neutralizing effect of fly ash (FA) as a stabilizing material AMD. Field plot was constructed in a coal waste depot which has caused aluminium-whitening adjacent to the stream. Different mixing ratios of FA were applied on a top of the soil, and then the physicochemical properties of runoff and soil were monitored. Constructed plots were as following: control (mine waste only (W)), mine waste + 20% ($w\;w^{-1}$)of FA (WC20M), mine waste + 40% ($w\;w^{-1}$)of FA (WC40M), and WC40M dressed with a fresh soil at the top (WC40MD). Result showed that initial pH of runoff in control was 5.09 while that in WC40M (7.81) was significantly increased. For a plot treated with WC40M, the concentration of Al in runoff was decreased to $0.22mg\;L^{-1}$ compared to the W as the control ($4.85mg\;L^{-1}$). Moreover, the concentration of Fe was also decreased to less than half at the WC40M compared to the control. Application of FA can be useful for neutralizing AMD and possibly minimizing adverse effect of AMD in mining area.

• Agricultural and Biosystems Engineering
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• v.6 no.1
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• pp.27-33
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• 2005

Soy protein meat analog was produced using a twin-screw extruder attached with a cooling die. Heat transfer analysis was performed for cooling dies with various die sizes at the four different moisture contents of feed during extrusion process. The experimental design consisted of two cooling die widths (30 and 60 mm), three cooling die lengths (100, 200, and 300 mm), four product moisture contents (71.2, 67.0, 61.6 and 55.8%), and water and water plus ethylene glycol as cooling material. When water was used as cooling medium, the values of equivalent overall heat transfer coefficient $(U_e)$ for each die width of 30 and 60 mm were in the range of 187.0 - 341.4 and $358.5-191.6W/m^2^{\circ}C$ depending on the size of die length. Convective heat transfer coefficients between cooling water and inside die wall of cooling channel $(h_c)$ for both die widths of 30 and 60 mm were 588.5, 416.1, and $339.8W/m^2^{\circ}C$ for each die length of 100, 200, and 300 mm. Convective heat transfer coefficients between product and inside die wall of product channel $(h_p)$ for each die width of 30 and 60 mm were in the range of $434.6-888.1W/m^2^{\circ}C$ and $460.7-1014.5W/m^2^{\circ}C$ depending on the size of die length. When water plus ethylene glycol was used as cooling medium, the values of $U_e$ were in the range of $143.9-319.6W/m^2^{\circ}C$ and $177.8-332.7W/m^2^{\circ}C$ for each die width of 30 and 60 mm depending on the size of die length.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.13 no.3
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• pp.214-219
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• 2000

In this paper the structural dielectric and piezoelectric properties of Pb［(M $g_{1}$2// $W_{1}$2/)$_{x}$-(N $i_{1}$3//N $b_{2}$3/)$_{0.15-x-(Zr_{0.5})}$ $Ti_{0.5}$)$_{0.85}$］ $O_3$ (x=0.0~0.10) ceramic were investigated with the substitution of Pb(M $g_{1}$2// $W_{1}$2/) $O_3$. According to the substitution of Pb(M $g_{1}$2//W/1/2/) $O_3$ curie temperatures were slightly decrease due to the decrease of the tetrag-onality of crystal structure and coercive fields were decreased. Up to the substitution of Pb(M $g_{1}$2// $W_{1}$2/) $O_3$ 3mol%,remnant polarization dielectric constant piezoelectric constant were increased. Dielectric constant and electro-mechanical coupling factor( $k_{p}$, $k_{31}$ ) were appeared the highest value of 2230, 0.64, and 0.38 and piezoelectric constant( $d_{33}$ , $d_{31}$ ) was the largest value of 418, 202($\times$10$^{-12}$ /C/N), respectively, when the substitution amount of Pb(M $g_{1}$2// $W_{1}$2/N) respectively, when the substitution amount of Pb(M $g_{1}$2// $W_{1}$2/) $O_3$ was 3mol%.s 3mol%.%.

• IT SoC Magazine
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• s.3
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• pp.35-37
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• 2004

본 연구팀이 Hynix 0.35um CMOS 4M 2P 공정을 사용하여 제작한 민수용 DDFS (DAC를 포함한 single chip)는 DC부터 100MHz 까지 사용할 수 있으며(BW=100MHz) frequency 변환속도 약 30nS, 주파수해상도 0.0745Hz, 그리고 소비 전력은 120MHz 클럭에서 약 200mW이다. 본고에서는 언급하지 않았지만, 본 연구팀이 별도의 설계로 진행된 군수용 DDFS의 경우, 출력주파수는 DC부터 320MHz 까지 가능하고 소비 전력은 800MHz 클럭에서 약 400mW이다. 이처럼 DDFS는 특성 자체의 우수성 뿐 아니라, 각종 멀티미디어 기기 및 통신시스템의 급격한 디지털화 추세로 인해 주파수합성기도 디지털화 함으로써 VLSI화가 용이하고, 이에 따라 S/W에 의한 다기능화 (programmability), 응용성의 극대화, 및 저가격화를 추구할 수 있다는 점에서 주목해야 할 분야이다. 특히 반도체기술의 발전으로 지금까지 DDFS 구현의 가장 큰 장애로 대두되던 DAC의 고속화가 부분적으로 가능해지면서 (TTL-to-ECL interface 부가회로가 별도로 필요없이 직접적인 연결), DDFS의 시장 전망을 더욱 밝게 하고 있다.