• Title/Summary/Keyword: P-type Si

Search Result 952, Processing Time 0.029 seconds

Computer simulation for the effects of inserting the textured ZnO and buffer layer in the rear side of ZnO/nip-SiC: H/metal type amorphous silicon solar cells (Zno/nip-SiC:H/금속기판 구조 비정질 실리콘 태양전지의 후면 ZnO 및 완충층 삽입 효과에 대한 컴퓨터 수치해석)

  • Jang, Jae-Hoon;Lim, Koeng-Su
    • Proceedings of the KIEE Conference
    • /
    • 1994.07b
    • /
    • pp.1277-1279
    • /
    • 1994
  • In the structure of ZnO/nip-SiC: H/metal substrate amorphous silicon (a-Si:H) solar cells, the effects of inserting a rear textured ZnO in the p-SiC:H/metal interface and a graded bandgap buffer layer in the i/p-SiC:H have been analysed by computer simulation. The incident light was taken to have an intensity of $100mW/cm^2$(AM-1). The thickness of the a-Si:H n, ${\delta}$-doped a-SiC:H p, and buffer layers was assumed to be $200{\AA},\;66{\AA}$, and $80{\AA}$, respectively. The scattering coefficients of the front and back ZnO were taken to be 0.2 and 0.7, respectively. Inserting the rear buffer layer significantly increases the open circuit voltage($V_{oc}$) due to reduction of the i/p interface recombination rate. The use of textured ZnO markedly improves collection efficiency in the long wavelengths( above ${\sim}550nm$ ) by back scattering and light confinement effects, resulting in dramatic enhancement of the short circuit current density($J_{sc}$). By using the rear buffer and textured ZnO, the i-layer thickness of the ceil for obtaining the maximum efficiency becomes thinner(${\sim}2500{\AA}$). From these results, it is concluded that the use of textured ZnO and buffer layer at the backside of the ceil is very effective for enhancing the conversion efficiency and reducing the degradation of a-Si:H pin-type solar cells.

  • PDF

Anodic Oxidation of Silicon in EPW Solution (EPW 용액에서의 실리콘 양극 산화막 형성에 관한 연구)

  • Bu, Jong-Uk;Kim, Seon-Mi;Kim, Seung-Hui;Kim, Seong-Tae;Gwon, Suk-In
    • Journal of the Korean Vacuum Society
    • /
    • v.2 no.2
    • /
    • pp.181-187
    • /
    • 1993
  • We have studied the anodic oxidation of silicon in the anisotropic etchant of EPW(Ethylenediamine, Pyrocatechol and Water) solution using the cyclic polarization technique. The samples have been characterized by means of X-ray photoelectron spectroscopy(XPS) and secondary ion mass spectrometry (SIMS). The results of cyclic polarization experiments show that the anodic oxides formed on p- and n-type silicon wafers break down at the same potential while breakdown does not occur up to open circuit potential in the case of $p^+$-Si. Strong etch-resistance of $p^+$-XPS. SIMS depth profiles suggest that the critical concentration of boron for etch-stop to occur appears to be much higher than what is widely believed.

  • PDF

Behavior of Na-A Type Zeolite from Melting Slag in its Hydrothermal Synthesis (용융(熔融)슬래그로부터 Na-A형(型) 제올라이트의 수열합성(水熱合成) 거동(擧動)에 대(對)한 고찰(考察))

  • Lee, Sung-Ki;Bae, In-Koon;Jang, Young-Nam;Chae, Soo-Chun;Ryu, Kyoung-Won
    • Resources Recycling
    • /
    • v.17 no.4
    • /
    • pp.57-65
    • /
    • 2008
  • The behavior of Na-A type zeolite formed in hydrothermal synthesis of melting slag from municipal incineration ash has been investigated with varying synthesis time and $SiO_2/Al_2O_3$ ratio. Sodium silicate and sodium aluminate feed was found to initially form nuclei of Na-A type zeolite in the behavioral study of the reaction products with different synthesis times. As the synthesis time increased, the nuclei have grown to Na-A type zeolite crystals by reacting with $SiO_2$ and $Al_2O_3$ dissolved from the melting slag. The hydrothermal synthesis was completed in 10 hr in the $SiO_2/Al_2O_3$ ratio of 1.38 and after that time, the Na-A type zeolite formed was dissolved and transformed into hydroxysodalite. Only Na-A type zeolite was formed in the $SiO_2/Al_2O_3$ ratio ranging 0.80 to 1.96, whereas Na-P type zeolite as well as Na-A type was formed in the $SiO_2/Al2O_3$ ratio of 2.54.

Low resistivity ohmic Pt/Si/Ti contacts to p-type 4H-SiC (Pt/Si/Ti P형 4H-SiC 오옴성 접합에서 낮은 접촉 저항에 관한 연구)

  • Yang, S.J.;Lee, J.H.;Nho, I.H.;Kim, C.G.;Cho, N.I.;Jung, K.H.;Kim, E.D.;Kim, N.K.
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
    • /
    • 2001.11b
    • /
    • pp.521-524
    • /
    • 2001
  • In this letter. we report on the investigation of Ti. Pt/Si/Ti Ohmic contacts to p-type 4H-SiC. The contacts were formed by a 2-step vacuum annealing at $500^{\circ}C$ for 1h. $950^{\circ}C$ for 10 min respectively. The contact resistances were measured using the transmission line model method. which resulted in specific contact resistivities in the $3.5{\times}10^{-3}$ and $6.2{\times}10^{-4}ohm/cm^{2}$, and the physical properties of the contacts were examined using x-ray diffraction. microscopy. AES(auger electron spectroscopy). AES analysis has shown that, at this anneal temperature, there was a intermixing of the Ti and Si. migration of into SiC. Overlayer of Pt had the effect of decreasing the specific contact resistivity and improving the surface morphology of the annealed contact.

  • PDF

Low resistivity ohmic Pt/Si/Ti contacts to p-type 4H-SiC (Pt/Si/Ti P형 4H-SiC 오옴성 접합에서 낮은 접촉 저항에 관한 연구)

  • 양성준;이주헌;노일호;김창교;조남인;정경화;김은동;김남균
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
    • /
    • 2001.11a
    • /
    • pp.521-524
    • /
    • 2001
  • In this letter, we report on the investigation of Ti, Pt/Si/Ti Ohmic contacts to p-type 4H-SiC. The contacts were formed by a 2-step vacuum annealing at 500$^{\circ}C$ for 1h, 950$^{\circ}C$ for 10 min respectively. The contact resistances were measured using the transmission line model method, which resulted in specific contact resistivities in the 3.5x10$\^$-3/ and 6.2x10$\^$-4/ ohm/$\textrm{cm}^2$, and the physical properties of the contacts were examined using x-ray diffraction, microscopy, AES(auger electron spectroscopy). AES analysis has shown that, at this anneal temperature, there was a intermixing of the Ti and Si, migration of into SiC. Overlayer of Pt had the effect of decreasing the specific contact resistivity and improving the surface morphology of the annealed contact.

  • PDF

A Strong Dependence of the P-P Bond Length on the Transition Metal Component in ThCr2Si2-Type Phosphides CaM2P2 (M = Fe, Ni): The Influence of d Band Position and σp* Mixing

  • Kang, Dae-Bok
    • Bulletin of the Korean Chemical Society
    • /
    • v.24 no.8
    • /
    • pp.1215-1218
    • /
    • 2003
  • An analysis of the bonding situation in CaM₂P₂ (M=Fe, Ni) with ThCr₂Si₂ structure is made in terms of DOS and COOP plots. The main contributions to covalent bonding are due to M-P and P-P interactions in both compounds. Particularly, the interlayer P-P bonding by variation in the transition metal is examined in more detail. It turns out that the shorter P-P bonds in CaNi₂P₂ form as a result of the decreasing electron delocalization into ${{\sigma}_p}^*$ of P₂ due to the weaker bonding interaction between the metal d and ${{\sigma}_p}^*$ as the metal d band is falling from Fe to Ni.

High Performance p-type SnO thin-film Transistor with SiOx Gate Insulator Deposited by Low-Temperature PECVD Method

  • U, Myeonghun;Han, Young-Joon;Song, Sang-Hun;Cho, In-Tak;Lee, Jong-Ho;Kwon, Hyuck-In
    • JSTS:Journal of Semiconductor Technology and Science
    • /
    • v.14 no.5
    • /
    • pp.666-672
    • /
    • 2014
  • We have investigated the gate insulator effects on the electrical performance of p-type tin monoxide (SnO) thin-film transistors (TFTs). Various SnO TFTs are fabricated with different gate insulators of a thermal $SiO_2$, a plasma-enhanced chemical vapor deposition (PECVD) $SiO_x$, a $150^{\circ}C$-deposited PEVCD $SiO_x$, and a $300^{\circ}C$-deposited PECVD $SiO_x$. Among the devices, the one with the $150^{\circ}C$-deposited PEVCD $SiO_x$ exhibits the best electrical performance including a high field-effect mobility ($=4.86cm^2/Vs$), a small subthreshold swing (=0.7 V/decade), and a turn-on voltage around 0 (V). Based on the X-ray diffraction data and the localized-trap-states model, the reduced carrier concentration and the increased carrier mobility due to the small grain size of the SnO thin-film are considered as possible mechanisms, resulting in its high electrical performance.

A Study on the Fabrication of p-type poly-Si Thin Film Transistor (TFT) Using Sequential Lateral Solidification(SLS) (SLS 공정을 이용한 p-type poly-Si TFT 제작에 관한 연구)

  • Lee, Yun-Jae;Park, Jeong-Ho;Kim, Dong-Hwan
    • The Transactions of the Korean Institute of Electrical Engineers C
    • /
    • v.51 no.6
    • /
    • pp.229-235
    • /
    • 2002
  • This paper presents the fabrication of polycrystalline thin film transistor(TFT) using sequential lateral solidification(SLS) of amorphous silicon. The fabricated SLS TFT showed high Performance suitable for active matrix liquid crystal display(AMLCD). The SLS process involves (1) a complete melting of selected area via irradiation through a patterned mask, and (2) a precisely controlled pulse translation of the sample with respect to the mask over a distance shorter than the super lateral growth(SLG) distance so that lateral growth extended over a number of iterative steps. The SLS experiment was performed with 550$\AA$ a-Si using 308nm XeCl laser having $2\mu\textrm{m}$ width. Irradiated laser energy density is 310mJ/$\textrm{cm}^2$ and pulse duration time was 25ns. The translation distance was 0.6$\mu$m/pulse, 0.8$\mu$m/pulse respectively. As a result, a directly solidified grain was obtained. Thin film transistors (TFTs) were fabricated on the poly-Si film made by SLS process. The characteristics of fabricated SLS p -type poly-Si TFT device with 2$\mu\textrm{m}$ channel width and 2$\mu\textrm{m}$ channel length showed the mobility of 115.5$\textrm{cm}^2$/V.s, the threshold voltage of -1.78V, subthreshold slope of 0.29V/dec, $I_{off}$ current of 7$\times$10$^{-l4}$A at $V_{DS}$ =-0.1V and $I_{on}$ / $I_{off}$ ratio of 2.4$\times$10$^{7}$ at $V_{DS}$ =-0.1V. As a result, SLS TFT showed superior characteristics to conventional poly-Si TFTs with identical geometry.y.y.y.

Processes For Fabricating Planar p-n Diodes and Planar n-p-n Transistors (푸래너.다이오드와 트랜지스터의 시작[제I보])

  • Jeong, Man-Yeong;An, Byeong-Seong;Kim, Jun-Ho
    • Journal of the Korean Institute of Telematics and Electronics
    • /
    • v.3 no.2
    • /
    • pp.2-9
    • /
    • 1966
  • fabricating processes of silicon planar n-p-n transistors are described. These processes include materical preparation, oxidation, photoresist, boron diffusion, phosphorous diffusion, and aluminium metalizing. Boron layer has been diffused in n type silicon from B2O3-SiO2 source using the box method, Phosporous layer has been diffused from P2O5-SiO2 source with the same method. The planar diodes are also fabricated by the processes described above.

  • PDF

The Dependence of Substrate on Ag Photodoping into Amorphous GeSe Thin Films using Holographic Method (비정질 GeSe 박막으로의 은-광도핑에 대한 기판의존성)

  • Yeo, Jong-Bin;Yun, Sang-Don;Lee, Hyun-Yong
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
    • /
    • v.20 no.10
    • /
    • pp.852-858
    • /
    • 2007
  • The dependence of substrate on the Ag photodoping phenomenon into amonhous $({\alpha}-)$ GeSe thin film has been investigated using holographic method. A 442 nm HeCd laser was utilized as a light source for the holographic exposure and a 632.8 nm HeNe laser to measure the variation of diffraction efficiency $(\eta)$ in real time. The films (Ag and ${\alpha}-GeSe$) were thermally deposited on the substrates, i.e. p-type Si(100), n-type Si(100) and slide glass. The sample structures prepared were two types: type I (Ag/${\alpha}$-SeGe/substrate) and type II (${\alpha}$-SeGe/Ag/substrate). The $\eta$ kinetics comprised to be three steps in which $\eta$ initially increases, is saturated to be maximized $(\eta_M)$, and then decreases relatively gradually. For the same substrate, the $\eta_M$ values of the type II were higher than those of type I. In addition, the type II exhibited the highest $\eta_M$ for p-type Si substrate, while that in type I was observed for n-type Si substrate. These tendency is explained by the diffusion of minority carrier in the films and the change of magnitude and direction in internal fields generated at the film interfaces. Atomic-force-microscope (AFM) was used to observe relief-type grating patterns.