• Proceedings of the Korean Vacuum Society Conference
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• 2014.02a
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• pp.273.2-273.2
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• 2014

Sputtering process has been widely used in Si-based semiconductor industry and it is also an ideal method to deposit transparent oxide materials for thin-film transistors (TFTs). The oxide films grown at low temperature by conventional RF sputtering process are typically amorphous state with low density including a large number of defects such as dangling bonds and oxygen vacancies. Those play a crucial role in the electron conduction in transparent electrode, while those are the origin of instability of semiconducting channel in oxide TFTs due to electron trapping. Therefore, post treatments such as high temperature annealing process have been commonly progressed to obtain high reliability and good stability. In this work, the scheme of electron-assisted RF sputtering process for high quality transparent oxide films was suggested. Through the additional electron supply into the plasma during sputtering process, the working pressure could be kept below $5{\times}10-4Torr$. Therefore, both the mean free path and the mobility of sputtered atoms were increased and the well ordered and the highly dense microstructure could be obtained compared to those of conventional sputtering condition. In this work, the physical properties of transparent oxide films such as conducting indium tin oxide and semiconducting indium gallium zinc oxide films grown by electron-assisted sputtering process will be discussed in detail. Those films showed the high conductivity and the high mobility without additional post annealing process. In addition, oxide TFT characteristics based on IGZO channel and ITO electrode will be shown.

• Proceedings of the Korean Vacuum Society Conference
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• 2015.08a
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• pp.192.1-192.1
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• 2015

We demonstrated the nonvolatile memory functionality of nano-crystalline silicon (nc-Si) and InGaZnOxide (IGZO) thin film transistors (TFTs) using mobile protons that are generated by very short time hydrogen neutral beam (H-NB) treatment in gate insulator (SiO2). The whole memory fabrication process kept under $50^{\circ}C$ (except SiO2 deposition process; $300^{\circ}C$). These devices exhibited reproducible hysteresis, reversible switching, and nonvolatile memory behaviors in comparison with those of the conventional FET devices. We also executed hydrogen treatment in order to figure out the difference of mobile proton generation between PECVD and H-NB CVD that we modified. Our study will further provide a vision of creating memory functionality and incorporating proton-based storage elements onto a probability of next generation flexible memorable electronics such as low power consumption flexible display panel.

• Proceedings of the Korean Vacuum Society Conference
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• 2015.08a
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• pp.204.1-204.1
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• 2015

We studied the electrical properties and gate bias stress (GBS) stability of thin film transistors (TFTs) with multi-stacked InZnO layers. The InZnO TFTs were fabricated via solution process and the In:Zn molar ratio was 1:1. As the number of InZnO layers was increased, the mobility and the subthreshold swing (S.S) were improved, and the threshold voltage of TFT was reduced. The TFT with three-layered InZnO showed high mobility of $21.2cm^2/Vs$ and S.S of 0.54 V/decade compared the single-layered InZnO TFT with $4.6cm^2/Vs$ and 0.71 V/decade. The three-layered InZnO TFTs were relatively unstable under negative bias stress (NBS), but showed good stability under positive bias stress (PBS).

• Proceedings of the Materials Research Society of Korea Conference
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• 2003.03a
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• pp.126-126
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• 2003

유기트랜지스터에 관한 연구는 1980년 이후부터 시작되었으나 근래에 들어 전 세계적으로 본격적인 연구가 진행되고 있다. 제작공정이 간단하고 비용이 저렴하며 충격에 의해 깨지지 않고 구부리거나 접을 수 있는 전자 회로 기판이 미래의 산업에 필수적인 요소가 될 것으로 예상되고 있으며 이러한 요구를 충족시킬 수 있는 유기트랜지스터의 개발은 아주 중요한 연구분야로 대두되고 있다. 본 연구에서는 표면처리에 따른 contact angle, I-V 특성곡선, 표면 morphology 등의 결과로부터 dry cleaning 한 것이 wet cleaning한 것보다 왜 좋은지를 논하고자 한다. 먼저 N-type SiO$_2$ 기판을 이용하여 back면의 oxide층을 제거한 후, back gate용으로 사용하기 위하여 sputtering장치로 Au/Cr을 증차하였다. 그리고 기판에 앞면을 photolithography 공정을 이용하여 Au/Cr를 1000$\AA$ 증착 하여 source-, drain-eldctrode를 제조하였다. 그리고 SiO$_2$ 기판의 표면처리를 달리하여 그 위에 유기박막을 증착하여 특성을 비교하였다.

• 한국정보디스플레이학회:학술대회논문집
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• 2006.08a
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• pp.695-698
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• 2006

The photosensitive poly-siloxane material used as the passivation layers for the conventional back channel etched (BCE) thin film transistors (TFTs) has been investigated. Through the organic material, the TFT array fabrication process can be reduced and higher aperture ratio can be achieved for higher LCD panel performance. The interface between the organic passivation layer and the back channel of the amorphous active region has been improved by the back channel oxygen treatment and the devices exhibits lower leakage current than the conventional silicon nitride passivation layer of BCE TFTs. The leakage currents between Indium-tin-oxide (ITO) pixels and the TFT devices and its mechanism have also been investigated in this paper.

• 한국정보디스플레이학회:학술대회논문집
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• 2006.08a
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• pp.190-193
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• 2006

we implemented pentacene TFTs able to operate at low voltage less than 2V by using ultrathin Al2O3 layer as a gate insulator. The OTFTs exhibited a mobility of $0.27{\pm}0.05\;cm^2/Vs$, an outstanding subthreshold slope of $0.109{\pm}0.027$, and an on/off current ratio of $2.87{\pm}1.07{\times}10^4$. OTFT operated at low voltage, producing 3.5uA at $V_GS$= 2V and $V_DS$= 1.5V.

• Journal of IKEEE
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• v.25 no.3
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• pp.501-505
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• 2021

In this study, we fabricated amorphous indium-tin-gallium-zinc-oxide thin-film transistors (a-ITGZO TFTs) with gate dielectrics of HfO₂ and the mixed layers of HfO₂ and Al₂O₃, and investigated the effect of gate dielectric on electrical characteristics of a-ITGZO TFTs. When only HfO₂ was used as the gate dielectric, the mobility and subthreshold swing (SS) were 32.3 cm²/Vs and 206 mV/dec. For the a-ITGZO TFTs with gate dielectric made of HfO₂ and Al₂O (2:1, 1:1), the mobilities and SS were 26.4 cm²/Vs (2:1), 16.8 cm²/Vs(1:1), 160 mV/dec (2:1) and 173 mV/dec (1:1). On the other hand, the hysteresis window shown in transfer curves of the a-ITGZO TFTs was lessened from 0.60 to 0.09 V by the increase of Al₂O₃ ratio in gate dielectric, indicating that the interface trap density between the gate dielectric and channel layer decreases due to Al₂O₃.

• Proceedings of the Korean Vacuum Society Conference
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• 2014.02a
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• pp.344-344
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• 2014

Transparent amorphous oxide semiconductors such as a In-Ga-Zn-O (a-IGZO) have advantages for large area electronic devices; e.g., uniform deposition at a large area, optical transparency, a smooth surface, and large electron mobility >10 cm2/Vs, which is more than an order of magnitude larger than that of hydrogen amorphous silicon (a-Si;H).1) Thin film transistors (TFTs) that employ amorphous oxide semiconductors such as ZnO, In-Ga-Zn-O, or Hf-In-Zn-O (HIZO) are currently subject of intensive study owing to their high potential for application in flat panel displays. The device fabrication process involves a series of thin film deposition and photolithographic patterning steps. In order to minimize contamination, the substrates usually undergo a cleaning procedure using deionized water, before and after the growth of thin films by sputtering methods. The devices structure were fabricated top-contact gate TFTs using the a-IGZO films on the plastic substrates. The channel width and length were 80 and 20 um, respectively. The source and drain electrode regions were defined by photolithography and wet etching process. The electrodes consisting of Ti(15 nm)/Al(120 nm)/Ti(15nm) trilayers were deposited by direct current sputtering. The 30 nm thickness active IGZO layer deposited by rf magnetron sputtering at room temperature. The deposition condition is as follows: a rf power 200 W, a pressure of 5 mtorr, 10% of oxygen [O2/(O2+Ar)=0.1], and room temperature. A 9-nm-thick Al2O3 layer was formed as a first, third gate insulator by ALD deposition. A 290-nm-thick SS6908 organic dielectrics formed as second gate insulator by spin-coating. The schematic structure of the IGZO TFT is top gate contact geometry device structure for typical TFTs fabricated in this study. Drain current (IDS) versus drain-source voltage (VDS) output characteristics curve of a IGZO TFTs fabricated using the 3-layer gate insulator on a plastic substrate and log(IDS)-gate voltage (VG) characteristics for typical IGZO TFTs. The TFTs device has a channel width (W) of $80{\mu}m$ and a channel length (L) of $20{\mu}m$. The IDS-VDS curves showed well-defined transistor characteristics with saturation effects at VG>-10 V and VDS>-20 V for the inkjet printing IGZO device. The carrier charge mobility was determined to be 15.18 cm^2 V-1s-1 with FET threshold voltage of -3 V and on/off current ratio 10^9.

• 한국정보디스플레이학회:학술대회논문집
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• 2009.10a
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• pp.998-1001
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• 2009

A new flexible TFT backplane structure with improved mechanical reliability is proposed. Amorphous indium-gallium-zinc-oxide (a-IGZO) thin film transistors based on this structure have been fabricated on a polyimide substrate, and the resultant mechanical durability has been evaluated in a cyclic bending test. The panel can withstand 10,000 bending cycles at a bending radius of 5 mm without any noticeable TFT degradation. After 10K bending cycles, the change of threshold voltage, mobility, sub-threshold slope, and gate leakage current were only -0.22V, -0.13$cm^2$/V-s, -0.05V/decade, and $-3.05{\times}10^{-13}A$, respectively.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.02a
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• pp.434-435
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• 2012

Plasma enhanced chemical vapor deposition (PECVD) silicon dioxide thin films have many applications in semiconductor manufacturing such as inter-level dielectric and gate dielectric metal oxide semiconductor field effect transistors (MOSFETs). Fundamental chemical reaction for the formation of SiO2 includes SiH4 and O2, but mixture of SiH4 and N2O is preferable because of lower hydrogen concentration in the deposited film [1]. It is also known that binding energy of N-N is higher than that of N-O, so the particle generation by molecular reaction can be reduced by reducing reactive nitrogen during the deposition process. However, nitrous oxide (N2O) gives rise to nitric oxide (NO) on reaction with oxygen atoms, which in turn reacts with ozone. NO became a greenhouse gas which is naturally occurred regulating of stratospheric ozone. In fact, it takes global warming effect about 300 times higher than carbon dioxide (CO2). Industries regard that N2O is inevitable for their device fabrication; however, it is worthwhile to develop a marginable nitrous oxide free process for university lab classes considering educational and environmental purpose. In this paper, we developed environmental friendly and material cost efficient SiO2 deposition process by substituting N2O with O2 targeting university hands-on laboratory course. Experiment was performed by two level statistical design of experiment (DOE) with three process parameters including RF power, susceptor temperature, and oxygen gas flow. Responses of interests to optimize the process were deposition rate, film uniformity, surface roughness, and electrical dielectric property. We observed some power like particle formation on wafer in some experiment, and we postulate that the thermal and electrical energy to dissociate gas molecule was relatively lower than other runs. However, we were able to find a marginable process region with less than 3% uniformity requirement in our process optimization goal. Surface roughness measured by atomic force microscopy (AFM) presented some evidence of the agglomeration of silane related particles, and the result was still satisfactory for the purpose of this research. This newly developed SiO2 deposition process is currently under verification with repeated experimental run on 4 inches wafer, and it will be adopted to Semiconductor Material and Process course offered in the Department of Electronic Engineering at Myongji University from spring semester in 2012.