• Proceedings of the Korean Vacuum Society Conference
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• 2010.08a
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• pp.124-124
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• 2010

Currently, extreme ultraviolet lithography (EUVL) is being investigated for next generation lithography. EUVL is one of competitive lithographic technologies for sub-22nm fabrication of nano-scale Si devices that can possibly replace the conventional photolithography used to make today's microcircuits. Among the core EUVL technologies, mask fabrication is of considerable importance due to the use of new reflective optics having a completely different configuration compared to those of conventional photolithography. Therefore, new materials and new mask fabrication process are required for high performance EUVL mask fabrication. This study investigated the etching properties of SnO2 (Tin Oxide) as a new absorber material for EUVL binary mask. The EUVL mask structure used for etching is SnO2 (absorber layer) / Ru (capping / etch stop layer) / Mo-Si multilayer (reflective layer) / Si (substrate). Since the Ru etch stop layer should not be etched, infinitely high selectivity of SnO2 layer to Ru ESL is required. To obtain infinitely high etch selectivity and very low LER (line edge roughness) values, etch parameters of gas flow ratio, top electrode power, dc self - bias voltage (Vdc), and etch time were varied in inductively coupled Cl2/Ar plasmas. For certain process window, infinitely high etch selectivity of SnO2 to Ru ESL could be obtained by optimizing the process parameters. Etch characteristics were measured by on scanning electron microscopy (SEM) and X-ray photoelectron spectroscopy (XPS) analyses. Detailed mechanisms for ultra-high etch selectivity will be discussed.

• Journal of Electrical Engineering and Technology
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• v.6 no.2
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• pp.233-238
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• 2011

In the present work, a new approach is proposed for via interconnects of semiconductor devices, where multi-wall carbon nanotubes (MWCNTs) are used instead of conventional metals. In order to implement a selective growth of carbon nanotubes (CNTs) for via interconnect, the buried catalyst method is selected which is the most compatible with semiconductor processes. The cobalt catalyst for CNT growth is pre-deposited before via hole patterning, and to achieve the via etch stop on the thin catalyst layer (ca. 3nm), a novel 2-step etch scheme is designed; the first step is a conventional oxide etch while the second step chemically etches the silicon nitride layer to lower the damage of the catalyst layer. The results show that the 2-step etch scheme is a feasible candidate for the realization of CNT interconnects in conventional semiconductor devices.

• Journal of the Korean Vacuum Society
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• v.1 no.1
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• pp.190-197
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• 1992

In this study we have investigated physical and electrical properties of high temperature oxide (HTO) thin film using dichlorosilane (DCS) gas. This film had low etch rate and excellent step coverage, and its characteristics of Si-O bond were similar to those of thermal oxide. I-V curves also showed similar electrical properties to those of thermally grown oxide (SiO2) while time dependent dielectric breakdown (TDDB) results revealed 1/4 value of thermal oxide. However, defect density was measured to be much lower value than that of thermal oxide.

• Journal of Sensor Science and Technology
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• v.32 no.5
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• pp.328-333
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• 2023

This study experimentally verified the etch rate of the SiO₂ sacrificial layer etching process with a single etch hole using vapor-phase hydrogen fluoride (VHF) etching. To fabricate small-sized polysilicon etch holes, both circular and triangular pattern masks were employed. Etch holes were fabricated in the polysilicon thin film on the SiO₂ sacrificial layer, and VHF etching was performed to release the polysilicon thin film. The lateral etch rate was measured for varying etch hole sizes and sacrificial layer thicknesses. Based on the measured results, we obtained an approximate equation for the etch rate as a function of the etch hole size and sacrificial layer thickness. The etch rates obtained in this study can be utilized to minimize structural damage caused by incomplete or excessive etching in sacrificial layer processes. In addition, the results of this study provide insights for optimizing sacrificial layer etching and properly designing the size and spacing of the etch holes. In the future, further research will be conducted to explore the formation of structures using chemical vapor deposition (CVD) processes to simultaneously seal etch hole and prevent adhesion owing to polysilicon film vibration.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.11a
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• pp.83-83
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• 2008

Metal-oxide-silicon-on-insulator (MOSOI) structures were fabricated to study the effect caused by reactive ion etching (RIE) and sacrificial oxidation process on silicon-on-insulator (SOI) layer. The MOSOI capacitors with an etch-damaged SOI layer were characterized by capacitance-voltage (C-V) measurements and compared to the sacrificial oxidation treated samples and the reference samples without etching treatment. The measured C-V curves were compared to the numerical results from 2-dimensional (2-D) simulations. The measurements revealed that the profile of C-V curves significantly changes depending on the SOI surface condition of the MOSOI capacitors. The shift in the measured C-V curves, due to the difference of the fixed oxide charge ($Q_f$), together with the numerical simulation analysis and atomic force microscopy (AFM) analysis, allowed extracting the fixed oxide charges ($Q_f$) in the structures as well as 2-D carrier distribution profiles.

• Journal of Sensor Science and Technology
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• v.13 no.4
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• pp.264-269
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• 2004

This paper describes on an advanced technology of 3C-SiC/Si(100) wafer direct bonding using PECVD oxide to intermediate layer for SiCOI(SiC-on-Insulator) structure because it has an attractive characteristics such as a lower thermal stress, deposition temperature, more quick deposition rate and higher bonding strength than common used poly-Si and thermal oxide. The PECVD oxide was characterized by ATR-FTIR. The bonding strength with variation of HF pre treatment condition was measured by tensile strength measurement system. After etch-back using TMAH solution, roughness of 3CSiC surface crystallinity and bonded interface was measured and analyzed by AFM, XRD, and SEM respectively.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.11 no.4
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• pp.261-266
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• 1998

In developing the high density memory device, the etching of fine pattern is becoming increasingly important. Therefore, definition of ultra fine line and space pattern and minimization of damage and contamination are essential process. Also, the high density plasma in low operating pressure is necessary. The candidates of high density plasma sources are electron cyclotron resonance plasma, helicon wave plasma, helical resonator, and inductively coupled plasma. In this study, planar type magnetized inductively coupled plasma etcher has been built. The density and temperature of Ar plasma are measured as a function of rf power, flow rate, external magnetic field, and pressure. The oxide etch rate and selectivity to polysilicon are measured as the above mentioned conditions and self-bias voltage.

• Electrical & Electronic Materials
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• v.8 no.6
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• pp.774-779
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• 1995

Process optimization experiments based on the Taguchi method were performed in order to set up the optimal process conditions for the contact oxide etching process module which was built in order to be attached to the cluster system of multi-processing purpose. In order to compare with Taguchi method, the contact oxide etching process carried out with different process parameters(CHF$_{3}$/CF$_{4}$ gas flow rate, chamber pressure, RF power and magnetic field intensity). Optimal etching characteristics were evaluated in terms of etch rate, selectivity, uniformity and etched profile. In this paper, as a final analysis of experimental results the optimal etching characteristics were obtained at the process conditions of CHF3/CF4 gas flow rate = 72/8 sccm, chamber pressure = 50 mTorr, RF power = 500 watts, and magnetic field intensity = 90 gauss.

• Proceedings of the Korean Vacuum Society Conference
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• 2011.02a
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• pp.287-287
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• 2011

ITRS(international technology roadmap for semiconductors)에 따르면 MOS (metal-oxide-semiconductor)의 CD(critical dimension)가 45 nm node이하로 줄어들면서 poly-Si/SiO2를 대체할 수 있는 poly-Si/metal gate/high-k dielectric이 대두되고 있다. 일반적으로 metal gate를 식각시 정확한 CD를 형성시키기 위해서 plasma를 이용한 RIE(reactive ion etching)를 사용하고 있지만 PIDs(plasma induced damages)의 하나인 PICD(plasma induced charging damage)의 발생이 문제가 되고 있다. PICD의 원인으로 plasma의 non-uniform으로 locally imbalanced한 ion과 electron이 PICC(plasma induced charging current)를 gate oxide에 발생시켜 gate oxide의 interface에 trap을 형성시키므로 그 결과 소자 특성 저하가 보고되고 있다. 그러므로 본 연구에서는 이에 차세대 MOS의 metal gate의 식각공정에 HDP(high density plasma)의 ICP(inductively coupled plasma) source를 이용한 중성빔 시스템을 사용하여 PICD를 줄일 수 있는 새로운 식각 공정에 대한 연구를 하였다. 식각공정조건으로 gas는 HBr 12 sccm (80%)와 Cl2 3 sccm (20%)와 power는 300 w를 사용하였고 200 eV의 에너지로 식각공정시 TEM(transmission electron microscopy)으로 TiN의 anisotropic한 형상을 볼 수 있었고 100 eV 이하의 에너지로 식각공정시 하부층인 HfO2와 높은 etch selectivity로 etch stop을 시킬 수 있었다. 실제 공정을 MOS의 metal gate에 적용시켜 metal gate/high-k dielectric CMOSFETs의 NCSU(North Carolina State University) CVC model로 effective electric field electron mobility를 구한 결과 electorn mobility의 증가를 볼 수 있었고 또한 mos parameter인 transconductance (Gm)의 증가를 볼 수 있었다. 그 원인으로 CP(Charge pumping) 1MHz로 gate oxide의 inteface의 분석 결과 이러한 결과가 gate oxide의 interface trap양의 감소로 개선으로 기인함을 확인할 수 있었다.

• Applied Chemistry for Engineering
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• v.18 no.1
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• pp.24-28
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• 2007

The etching of zinc oxide (ZnO) thin films has been studied using a high density plasma in a $Cl_2/Ar$ gas. The etch characteristics of ZnO thin films were systematically investigated on varying $Cl_2$ concentration, coil rf power, dc-bias voltage, and gas pressure. With increasing $Cl_2$ concentration, the etch rate of ZnO thin film increased, the redeposition around the etched patterns decreased but the sidewall slope of the etched patterns slanted. As the coil rf power and dc-bias voltage increased, the etch rates of ZnO thin films increased and etch profiles of ZnO thin films were improved. With increasing gas pressure, the etch rate of ZnO thin films slightly increased but little change in etch profile was observed. Based on these results, the optimal etching conditions of ZnO thin film were selected. Finally, the etching of ZnO thin films with a high degree of anisotropy of approximately $75^{\circ}{\sim}80^{\circ}$ without the redepositions and residues was successfully achieved at the etching conditions of 20% $Cl_2$ concentration, coil rf power of 1000 W, dc-bias voltage of 400 V, and gas pressure of 5 mTorr.