• Korean Journal of Materials Research
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• v.5 no.6
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• pp.706-714
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• 1995

Silicon oxide thin films were deposited by remote plasma chemical vapor deposition (RPCYD). The effect of the operating variables, such as plasma power, deposition temperature and partial pressure of reactant on the material Properties of the silicon oxide film was investigated. By XPS, it was found out that the film was suboxide (O/Si<2) and small amount of nitrogen due to the plasma excitation was accumulated at the Si/SiO$_2$interface. The amount of dangling bonds at the Si/SiO$_2$interfaces were measured by ESR and the concentration of hydrogen bond was obtained by SIMS and FT-IR. The bond angle distribution(d$\theta$/$\theta$) was shown to be similiar to thermal oxide above 20$0^{\circ}C$ but the etch rate was higher than that of the thermal oxides due to the structural difference and the stress between silicon substrate and silicon oxide film.

• JSTS:Journal of Semiconductor Technology and Science
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• v.17 no.2
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• pp.260-264
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• 2017

Process variation effect on arch-structured gate stacked array (GSTAR) 3-D NAND flash is investigated. In case of arch-structured GSTAR, a shape of the arch channel is depending on an alignment of photo-lithography. Channel width fluctuates according to the channel hole alignment. When a shape of channel exceeds semicircle, channel width becomes longer, increasing drain current. However, electric field concentration on tunnel oxide decreases because less electric flux converges into a larger surface of tunnel oxide. Therefore, program efficiency is dependent on the process variation. Meanwhile, a radius of channel holes near the bottom side become smaller due to an etch slope. It also affects program efficiency as well as channel width. Larger hole radius has an advantage of higher drain current, but causes degradation of program speed.

• Proceedings of the Korean Vacuum Society Conference
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• 2015.08a
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• pp.132-132
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• 2015

Virtual metrology (VM) model based on plasma information (PI) parameter for C4F8 plasma-assisted oxide etching processes is developed to predict and monitor the process results such as an etching rate with improved performance. To apply fault detection and classification (FDC) or advanced process control (APC) models on to the real mass production lines efficiently, high performance VM model is certainly required and principal component regression (PCR) is preferred technique for VM modeling despite this method requires many number of data set to obtain statistically guaranteed accuracy. In this study, as an effective method to include the 'good information' representing parameter into the VM model, PI parameters are introduced and applied for the etch rate prediction. By the adoption of PI parameters of b-, q-factors and surface passivation parameters as PCs into the PCR based VM model, information about the reactions in the plasma volume, surface, and sheath regions can be efficiently included into the VM model; thus, the performance of VM is secured even for insufficient data set provided cases. For mass production data of 350 wafers, developed PI based VM (PI-VM) model was satisfied required prediction accuracy of industry in C4F8 plasma-assisted oxide etching process.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.06a
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• pp.88-89
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• 2009

In this paper, we investigated about wet cleaning effect as deep trench formation methods for Power chip devices. Deep trench structure was classified by two methods, PSU (Poly Stick Up) and Non-PSU structure. In this paper, we could remove residue defect during wet. cleaning after deep trench etch process for non-PSU structure device as to change wet cleaning process condition. V-SEM result showed void image at the trench bottom site due to residue defect and residue component was oxide by EDS analysis. In order to find the reason of happening residue defect, we experimented about various process conditions. So, defect source was that oxide film was re-deposited at trench bottom by changed to hydrophobic property at substrate during hard mask removal process. Therefore, in order to removal residue defect, we added in-situ SCI during hard mask removal process, and defect was removed perfectly. And WLR (Wafer Level Reliability) test result was no difference between normal and optimized process condition.

• 한국정보디스플레이학회:학술대회논문집
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• 2008.10a
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• pp.1097-1100
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• 2008

We demonstrate that the performance of amorphous indium-gallium-zinc-oxide (IGZO) thin-film transistors (TFT) can be optimized by controlling the interfaces between IGZO and sandwiching insulators and by proper deposition of IGZO layer. Specifically, contact and channel resistances are decreased by reducing IGZO bulk resistance and optimizing dry-etch process, respectively. Field-effect mobility ($\mu_{FE}$) and subthreshold gate swing (S) are further enhanced by fine-tuning IGZO deposition condition.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2005.11a
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• pp.65-66
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• 2005

Etching characteristics of $Ge_2Sb_2Te_5$ (GST) films were investigated using $Cl_2$/Ar inductively coupled plasma.We examined the etching characteristics such as etching rate and selectivity over oxide films of GST films using inductively coupled plasma (ICP) with various etching parameters such as $Cl_2$/Ar gas mixing ratios, ICP source power, pressure, and bias power. The maximum etch rate of GST film was $2,815{\AA}$/min and the selectivity higher than 12:1 over the oxide films was also obtained at the $Cl_2$ flow rates of 40 sccm.

• 한국정보디스플레이학회:학술대회논문집
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• 2007.08a
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• pp.145-148
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• 2007

The authors report on the fabrication of thin film transistors (TFTs) that use amorphous indium-gallium-zinc oxide (a-IGZO) channel and have the channel length (L) and width (W) patterned by dry etching. To prevent the plasma damage of active channel, a 100-nm-thckness $SiO_{x}$ by PECVD was adopted as an etch-stopper structure. IGZO TFT (W/L=10/50${\mu}m$) fabricated on glass exhibited the high performance mobility of $35.8\;cm^2/Vs$, a subthreshold gate voltage swing of $0.59V/dec$, and $I_{on/off}$ of $4.9{\times}10^6$. In addition, 4.1” transparent QCIF active-matrix organic light-emitting diode display were successfully fabricated, which was driven by a-IGZO TFTs.

• Journal of the Korean Vacuum Society
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• v.5 no.2
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• pp.169-174
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• 1996

The applications of the high density plasma sources to the etching in semiconductor fabrication process are actively studied because of the more strict requirement from the dry etching process due to shrinking down of the critical dimension. But in the oxide etching with the high density plasma sources, abundant fluorine atoms released from the flurocarbon feed gas make it difficult to get the highly selective $SiO_2/Si$ etching. In this study, to improve the $SiO_2/Si$ etch selectivity through the control of the radical loss channels, we propose the wall heating , one of methods of controlling loss mechanisms. With appearance mass spectroscopy(AMS) and actinometric optical emission spectroscopy(OES), the increase of both radicals impinging on the substrate and existing in bulk plasma, and the decrease of the fluorine atom with wall temperature are observed. As a result, a 40% improvement of the selectivity was achieved for the carbon rich feed gas.

• Journal of the Korean Crystal Growth and Crystal Technology
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• v.14 no.2
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• pp.47-49
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• 2004

Gate protection $SiN_x$ as an alternative to a conventional re-oxidation process in Dynamic Random Access Memory devices is investigated. This process can not only protect the gate electrode tungsten against oxidation, but also save the thermal budget due to the re-oxidation. The protection $SiN_x$ process is applied to the poly-Si gate, and its device performance is measured and compared with the re-oxidation processed poly-Si gate. The results on the gate dielectric integrity show that etch damage-curing capability of protection $SiN_x$ is comparable to the re-oxidation process. In addition, the hot carrier immunity of the $SiN_x$ deposited gate is superior to that of re-oxidation processed gate.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.34D no.12
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• pp.76-82
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• 1997

Chemical mechanical polishing (CMP) has become widely accepted for the planarization of multi-interconnect structures in semiconductor manufacturing. However, perfect planarization is not so easily ahieved because it depends on the pattern sensitivity, the large number of controllable process parameters, and the absence of a reliable process model, etc. In this paper, we realized the planarization of deposited oxide layers followed by metal (W) polishing as a replacement for tungsten etch-back process for via formation. Atomic force microscope (AFM) is used for the evaluation of pattern topography during CMP. As a result, AFM evaluation is very attractive compared to conventional methods for the measurment of planarity. mOreover, it will contribute to analyze planarization characteristics and establish CMP model.