• 제목/요약/키워드: Oxide Wafer

검색결과 314건 처리시간 0.04초

전자선 증착된 실리콘 산화막층을 이용한 직접 접합에 관한 연구 (A Study on the Direct Bonding Method using the E-Beam Evaporated Silicon dioxide Film)

  • 박흥우;주병권;이윤희;정성재;이남양;고근하;;박정호;오명환
    • 대한전기학회:학술대회논문집
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    • 대한전기학회 1996년도 하계학술대회 논문집 C
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    • pp.1988-1990
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    • 1996
  • In this work, we have grown or evaporated thermal oxide and E-beam oxide on the (100) oriented n-type silicon wafers, respectively and they were directly bonded with another silicon wafer after hydrophilization using solutions of three types of $HNO_3$, $H_{2}SO_{4}$ and $NH_{4}OH$. Changes of average surface roughness after hydrophilizations of the single crystalline silicon wafer, thermal oxide and E-beam evaporated silicon oxide were studied using atomic force microscope. Bonding interfaces of the bonded pairs were inspected using scanning electron microscope. Void and non-contact area of the bonded pairs were also inspected using infrared transmission microscope.

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Bonded SOI wafer의 top Si과 buried oxide layer의 결함에 대한 연구 (Characteristic Study for Defect of Top Si and Buried Oxide Layer on the Bonded SOI Wafer)

  • 김석구;백운규;박재근
    • 한국재료학회지
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    • 제14권6호
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    • pp.413-419
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    • 2004
  • Recently, Silicon On Insulator (SOI) devices emerged to achieve better device characteristics such as higher operation speed, lower power consumption and latch-up immunity. Nevertheless, there are many detrimental defects in SOI wafers such as hydrofluoric-acid (HF)-defects, pinhole, islands, threading dislocations (TD), pyramid stacking faults (PSF), and surface roughness originating from quality of buried oxide film layer. Although the number of defects in SOI wafers has been greatly reduced over the past decade, the turn over of high-speed microprocessors using SOI wafers has been delayed because of unknown defects in SOI wafers. A new characterization method is proposed to investigate the crystalline quality, the buried oxide integrity and some electrical parameters of bonded SOI wafers. In this study, major surface defects in bonded SOI are reviewed using HF dipping, Secco etching, Cu-decoration followed by focused ion beam (FIB) and transmission electron microscope (TEM).

산화 실리콘 막을 이용한 실리카 나노 와이어의 형성 : 산소 효과 (Formation of Silica Nanowires by Using Silicon Oxide Films: Oxygen Effect)

  • 윤종환
    • 새물리
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    • 제68권11호
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    • pp.1203-1207
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    • 2018
  • 본 연구에서는 산소 함유량이 다른 산화 실리콘 막을 사용하여 실리카 나노 와이어를 형성하고, 실리카 나노 와이어의 미세구조 및 물리적 특성을 Si 웨이퍼를 사용하여 형성된 실리카 나노 와이어와 비교 분석하였다. 산화 실리콘 막은 플라즈마 화학 기상 증착 방법을 사용하여 제조하였으며, 실리카 나노 와이어는 산화 실리콘 막 표면에 촉매 물질로 니켈 막을 진공 증착한 후 열처리를 통해 형성하였다. 산소 함유량이 약 50 at.% 이하의 산화 실리콘 막의 경우 나노 와이어 형성 메커니즘, 미세구조 및 물리적 특성 등에서 실리콘 웨이퍼의 경우와 거의 차이점이 없었으며, 특히 나노 와이어의 굵기의 균일성은 산화 실리콘 막에서 더 우수한 거동을 나타내었다. 이러한 결과는 저가로 양질의 실리카 나노 와이어를 제조하는 대체재로서 산화 실리콘 막의 유용성을 제시한다.

APPLICATIONS OF SOI DEVICE TECHNOLOGY

  • Ryoo, Kunkul
    • 한국표면공학회지
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    • 제29권5호
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    • pp.482-486
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    • 1996
  • The progress of microelectronics technology has been requiring agressive developments of device technologies. Also the requirements of the next generation devices is heading to the limits of their functions and materials, and hence asking the very specific silicon wafer such as SOI(Silicon On Insulator) wafer. The talk covers the dome stic and world-wide status of SOI device developments and applications. The presentation will also touch some predictions such as SOI device prgress schedules, impacts on the normal wafer developments, market sizes, SOI wafer prices, and so on. Finally it will cover technical aspects which are silicon oxide conditions for bonding, point defects and, surface contaminations. These points will be hopefully overcome by involved people in microelectronics industry.

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극한 환경 MEMS용 3C-SiC기판의 직접접합 (Direct Bonding of 3C-SiC Wafer for MEMS in Hash Environments)

  • 정연식;이종춘;정귀상
    • 대한전기학회:학술대회논문집
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    • 대한전기학회 2002년도 하계학술대회 논문집 C
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    • pp.2020-2022
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    • 2002
  • SiC direct bonding technology is very attractive for both SiCOI(SiC-on-insulator) electric devices and SiC-MEMS fileds because of its application possibility in harsh environements. This paper presents on pre-bonding according to HF pre-treatment conditions in SiC wafer direct bonding using PECVD oxide. The PECVD oxide was characterized by XPS and AFM, respectively. The characteristics of bonded sample were measured under different bonding conditions of HF concentration and applied pressure, respectively. The bonding strength was evaluated by tensile strength method. Components existed in the interlayer were analyzed by using FT-IR. The bond strength depends on the HF pre-treatment condition before pre-bonding (Min : 5.3 kgf/$cm^2{\sim}$ Max : 15.5 kgf/$cm^2$).

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Device Wafer의 평탄화와 AFM에 의한 평가

  • 김호윤;정해도
    • 한국정밀공학회:학술대회논문집
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    • 한국정밀공학회 1996년도 추계학술대회 논문집
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    • pp.167-171
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    • 1996
  • Chemical mechanical polishing (CMP) has become widely accepted for the planarization of multi-interconnect structures in semiconductor manufacturing. However, perfect planarization is not so easily achieved because it depends on the pattern sensitivity, the large number of controllable process parameters, and the absence of a reliable process model, etc. In this paper, we realized the planarization of deposited oxide layers followed by metal (W) polishing as a replacement for tungsten etchback process for via formation. Atomic force microscope (AFM) is used for the evaluation of pattern topography during CMP. As a result, AFM evaluation is very attractive compared to conventional methods for the measurement of planarity. Moreover, it will contribute to analyze planarization characteristics and establish CMP model.

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Determination of End Point for Direct Chemical Mechanical Polishing of Shallow Trench Isolation Structure

  • Seo, Yong-Jin;Lee, Kyoung-Jin;Kim, Sang-Yong;Lee, Woo-Sun
    • KIEE International Transactions on Electrophysics and Applications
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    • 제3C권1호
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    • pp.28-32
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    • 2003
  • In this paper, we have studied the in-situ end point detection (EPD) for direct chemical mechanical polishing (CMP) of shallow trench isolation (STI) structures without the reverse moat etch process. In this case, we applied a high selectivity $1n (HSS) that improves the silicon oxide removal rate and maximizes oxide to nitride selectivity Quite reproducible EPD results were obtained, and the wafer-to-wafer thickness variation was significantly reduced compared with the conventional predetermined polishing time method without EPD. Therefore, it is possible to achieve a global planarization without the complicated reverse moat etch process. As a result, the STI-CMP process can be simplified and improved using the new EPD method.

화합물 반도체 기판 위에 제작된 산화 알루미늄 광결정 특성 (Aluminum Oxide Photonic Crystals Fabricated on Compound Semiconductor)

  • 최재호;김근주;정미;우덕하
    • 한국전기전자재료학회:학술대회논문집
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    • 한국전기전자재료학회 2006년도 하계학술대회 논문집 Vol.7
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    • pp.77-78
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    • 2006
  • We fabricated photonic crystals on GaAs and GaN substrates. After anodizing the aluminium thin film in electrochemical embient, the porous alumina was implemented to the mask for reactive ion beam etching process of GaAs wafer. And photonic crystals in GaN wafer were also fabricated using electron beam nano-lithography process. The coated PMMA thin film with 200 nm-thickness on GaN surface was patterned with triangular lattice and etched out the GaN surface by the inductively coupled plasma source. The fabricated GaAs and GaN photonic crystals provide the enhanced intensities of light emission for the wavelengths of 858 and 450 nm, respectively. We will present the detailed dimensions of photonic crystals from SEM and AFM measurements.

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Atomic Layer Deposition에 의해 제조된 Cobalt Oxide 박막의 특성

  • 김재경;최규하;박광민;이원준;김진식
    • 한국진공학회:학술대회논문집
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    • 한국진공학회 2009년도 제38회 동계학술대회 초록집
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    • pp.207-207
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    • 2010
  • 휴대용 기기의 사용이 증가하면서 전지의 고용량화와 소형화가 요구되고 있다. 특히 의료용 센서 기기에서는 소형화가 매우 중요하며 인체에 해로운 물질로 구성되지 않는 것이 바람직하다. 최근 고체전해질을 사용하는 마이크로 배터리가 개발되고 있으나, 에너지 저장용량이 작아 응용분야가 제한적이다. Silicon wafer 위에 형성된 고단차의 3차원 박막 배터리를 형성한다면 표면적 증가에 의해 에너지 저장용량 역시 크게 증가할 것이다. 따라서 고단차의 3차원 구조위에 confomal한 박막을 형성하기 위해서는 기존 물리증착방법과는 달리 새로운 step coverage가 우수한 박막증착법이 필요하다. 본 연구에서는 atomic layer deposition(ALD)으로 박막 배터리의 cathode 물질인 $LiCoO_2$를 증착하기 위한 기초연구로서 cobalt oxide 박막의 ALD 공정을 연구하였다. Cobalt +2가 전구체와 $O_3$를 교대로 공급하여 박막을 증착하고 그 박막의 물리적, 화학적, 전기적 특성을 조사하였다. 이를 통해 exposure와 기판온도가 박막의 특성에 미치는 영향을 고찰하였다. 또한 pattern wafer위에 박막을 증착하여 step coverage를 조사하였다.

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Surface properties of Nb oxide thin films prepared by rf sputtering

  • 박주연;강용철
    • 한국진공학회:학술대회논문집
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    • 한국진공학회 2016년도 제50회 동계 정기학술대회 초록집
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    • pp.306.2-306.2
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    • 2016
  • Niobium oxide thin films were synthesized by reactive rf magnetron sputtering. The target was metallic niobium with 2 inch in diameter and the substrate was n-type Si wafer. To control the surface properties of the films, Nb oxide thin films were obtained at various mixing ratios of argon and oxygen gases. Nb oxide thin films were analyzed with alpha step, scanning electron microscopy (SEM), X-ray diffraction (XRD), and X-ray photoelectron spectroscopy (XPS). The result of alpha step showed that the thickness of Nb oxide thin films were decreased with increasing the oxygen gas ratios. SEM images showed that the granular morphology was formed at 0% of oxygen gas ratio and then disappeared at 20 and 75% of oxygen gas ratio. The amorphous Nb oxide was observed by XRD at all films. The oxidation state of Nb and O were studied with high resolution Ni 2p and O 1s XPS spectra. And the change in the chemical environment of Nb oxide thin films was investigated by XPS with Ar+ sputtering.

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