• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1998년도 추계종합학술대회 논문집
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• pp.601-604
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• 1998

NOX detecting gas sensors using TiO2 doped tungsten oxide semiconductor were prepared and their electrical and sensing characteristics have been investigated. In normal air condition, the sensors of WO3, TiO2 doped WO3 show grain boundary heights of 0.34 eV, 0.25 eV, respectively. The grain boundary barrier energy variation was increased by doping TiO2 into large variation of resistance to NOX gases. And doping the TiO2 4 wt.%, the particle size of WO3 polycrystal films showed higher sensitivity and better sorption characteristics to NOX gas than the pure WO3 films material in air at operating temperature of $350^{\circ}C.$ The TiO2 doped WO3 semiconductor gas sensor shows nano-sized particle size and good sensitivity to sub-ppm concentration of NOX.

• Journal of Electrical Engineering and Technology
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• 제6권2호
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• pp.233-238
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• 2011

In the present work, a new approach is proposed for via interconnects of semiconductor devices, where multi-wall carbon nanotubes (MWCNTs) are used instead of conventional metals. In order to implement a selective growth of carbon nanotubes (CNTs) for via interconnect, the buried catalyst method is selected which is the most compatible with semiconductor processes. The cobalt catalyst for CNT growth is pre-deposited before via hole patterning, and to achieve the via etch stop on the thin catalyst layer (ca. 3nm), a novel 2-step etch scheme is designed; the first step is a conventional oxide etch while the second step chemically etches the silicon nitride layer to lower the damage of the catalyst layer. The results show that the 2-step etch scheme is a feasible candidate for the realization of CNT interconnects in conventional semiconductor devices.

• KIEE International Transactions on Electrophysics and Applications
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• 제3C권2호
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• pp.66-69
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• 2003

Various semiconductor nanowires such as GaN, GaP, InP, Si$_3$N$_4$, SiO$_2$/Si, and SiC were coated conformally with aluminum oxide (Al$_2$O$_3$) layers by atomic layer deposition (ALD) using trimethylaluminum (TMA) and distilled water ($H_2O$) at a temperature of 20$0^{\circ}C$. Transmission electron microscopy (TEM) revealed that A1203 cylindrical shells conformally coat the semiconductor nanowires. This study suggests that the ALD of $Al_2$O$_3$ on nanowires is a promising method for preparing cylindrical dielectric shells for coaxially gated nanowire field-effect transistors.

• JSTS:Journal of Semiconductor Technology and Science
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• 제7권2호
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• pp.82-87
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• 2007

The electrical properties of metallic junction diodes and metallic source/drain (S/D) Schottky barrier metal-oxide-semiconductor field-effect transistor (SB-MOSFET) were simulated. By using the abrupt metallic junction at the S/D region, the short-channel effects in nano-scaled MOSFET devices can be effectively suppressed. Particularly, the effects of trap states at the metal-silicide/silicon interface of S/D junction were simulated by taking into account the tail distributions and the Gaussian distributions at the silicon band edge and at the silicon midgap, respectively. As a result of device simulation, the reduction of interfacial trap states with Gaussian distribution is more important than that of interfacial trap states with tail distribution for improving the metallic junction diodes and SB-MOSFET. It is that a forming gas annealing after silicide formation significantly improved the electrical properties of metallic junction devices.

• Preventive Nutrition and Food Science
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• 제7권1호
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• pp.33-36
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• 2002

A catalase from Micrococcus sp. isolated from soil was applied to degrade hydrogen Peroxide in wastewater from a semiconductor industry. The degradation rates of hydrogen peroxide increased with increasing reaction time and catalase concentrations in the reaction mixture. However, in the presence of aluminum chloride or chloride oxide used in detergent compounds, the degradation rate of hydrogen peroxide was not affected. Enzyme stabilizers and antifoam did not affect the degradation rates of hydrogen peroxide.

• 반도체디스플레이기술학회지
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• 제1권1호
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• pp.9-13
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• 2002

A polyimide-type electrostatic chuck (ESC) was fabricated for the application of holding 8-inch silicon wafers in the oxide etching equipment. For the fabrication of the unipolar ESC, core technologies such as coating of polyimide films and anodizing treatment of aluminum surface were developed. The polyimide films were prepared on top of thin coated copper substrates for the good electrical contacts, and the helium gas cooling technique was used for the temperature uniformity of the silicon wafers. The ESC was essentially working with an unipolar operation, which was easier to fabricate and operate compared to a bipolar operation. The chucking force of the ESC has been measured to be about 580 gf when the applied voltage was 1.5 kV, which was considered to be enough force to hold wafers during the dry etching processing. The employment of the ESC in etcher system could make 8% enhancement of the wafer processing yield.

• 반도체디스플레이기술학회지
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• 제13권1호
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• pp.63-66
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• 2014

ZnO is a wide bandgap (3.3 eV) semiconductor with high mobility and good optical transparency. However, off-current characteristics of ZnO thin-film transistor (TFT) need improvements. In this work we studied the variation in ZnO TFT current under different annealing conditions. Annealing usually modifies gas adsorption at grain boundaries of ZnO. When oxygen is adsorbed, electron density decreases due to strong electronegativity of the oxygen, and TFT current decreases as a result. Our experiments showed that current increased after vacuum annealing and decreased after air annealing. We explain that the change of off-current is caused by the desorption and adsorption of oxygen at the grain boundaries.

• 한국반도체및디스플레이장비학회:학술대회논문집
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• 한국반도체및디스플레이장비학회 2004년도 춘계학술대회 발표 논문집
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• pp.92-96
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• 2004

Scales, accumulated on semiconductor equipment parts during device fabrication processes, often lower equipment lifetime and production yields. Thus, many equipments parts have be cleaned regularly. In this study, an attempt to establish an effective process for the removal of scales on the sidewall of collimators in the chamber of sputter is made. The EDX analysis revealed that the scales are composed of Ti and TiN with the colummar structure. It was found that the heat-treatment at 700 for 1 min. after the oxide removal in the HF solution, and then etching in the HNO3 : H2SO4 : H2O =4:2:4 solution for 5.5 hrs at 67 was the most effective process for the scale removal.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1987년도 전기.전자공학 학술대회 논문집(I)
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• pp.420-423
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• 1987

Planarization in multilevel metallization is very important to smooth out topographic undulations by conductors, dielectrics, contacts, and vias. One of methods for planarizing interdielectrics, such as the etchback process of the double layer composed of the photoresist on the interdielectric low temperature oxide was introduced. The step heights of interdielectrics before and after etch-back process was measured by Scanning Electron Microscope, and the degree of planarization was analyzed, comparing the differences of the step heights. In this experiment, the degree of planarization was controlled up to about 0.9.

• 반도체디스플레이기술학회지
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• 제9권2호
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• pp.7-10
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• 2010

In this paper, we design a modem SoC (System on Chip) for low power consumption and high speed wireless communications. Among various schemes of high speed communications, an MB-OFDM (Multi Band-Orthogonal Frequency Division Multiplexing) UWB (Ultra-Wide-Band) chip is designed. The MB-OFDM uses wide-band frequency to provide high speed data rate. Additionally, the system imposes no interference to other services. The 90nm CMOS (Complementary Metal-Oxide Semiconductor) technology is used for the SoC design. Especially, power management mode is implemented to reduce the power consumption.