• 한국진공학회:학술대회논문집
• /
• 한국진공학회 2014년도 제46회 동계 정기학술대회 초록집
• /
• pp.346.2-346.2
• /
• 2014

To use the GaN based light-emitting diodes (LEDs) as solid state lighting sources, the improvement of light extraction and internal quantum efficiency is essential factors for high brightness LEDs. In this study, we suggested the new materials system of a zinc tin oxide (ZTO) layer formed on blue LED epi-structures to improve the light extraction. ZTO is a representative n-type oxide material consisted of ZnO and SnO system. Moreover, ZTO is one of the promising oxide semiconductor material. Even though ZTO has higher chemical stability than IGZO owing to its SnO2 content this has high mobility and high reliability. After formation of ZTO layer on p-GaN layer by using the spin coating method, structural and optical properties are investigated. The x-ray diffraction (XRD) measurement results show the successful formation of ZTO. The photoluminescence (PL) and absorption spectrum shows that it has 3.6-4.1eV band gap. Finally, the light extraction properties of ZTO/LED chip using electroluminescence (EL) measurement were investigated. The experimental and theoretical analyses were simultaneously conducted.

• 한국정보디스플레이학회:학술대회논문집
• /
• 한국정보디스플레이학회 2009년도 9th International Meeting on Information Display
• /
• pp.1582-1585
• /
• 2009

The effects of bias stress on spin-coated zinc tin oxide (ZTO) transistors are investigated. Applying a positive bias stress results in the displacement of the transfer curves in the positive direction without changing the field effect mobility or the subthreshold behavior. Device instability appears to be a consequence of the charging and discharging of temporal trap states at the interface and in the zinc tin oxide channel region.

• 한국재료학회:학술대회논문집
• /
• 한국재료학회 2009년도 춘계학술발표대회
• /
• pp.52.1-52.1
• /
• 2009

Cupric oxide (CuO) is a p-type semiconductor with band gap of ~1.7 eV and reported to be suitable for catalysis, lithium-copper oxide electrochemical cells, and gas sensors applications. The nanoparticles, plates and nanowires of CuO were found sensing to NO2, H2S and CO. In this work, we report about the comparison about hydrogen sensing of nano thin film and nanowires structured CuO deposited on single-walled carbon nanotubes (SWNTs). The thin film and nanowires are synthesized by deposition of Cu on different substrate followed by oxidation process. Nano thin films of CuO are deposited on thermally oxidized silicon substrate, whereas nanowires are synthesized by using a porous thin film of SWNTs as substrate. The hydrogen sensing properties of synthesized materials are investigated. The results showed that nanowires cupric oxide deposited on SWNTs showed higher sensitivity to hydrogen than those of nano thin film CuO did.

• 한국표면공학회지
• /
• 제33권4호
• /
• pp.217-221
• /
• 2000

The gate oxide thickness is becoming thinner and thinner in order to speed up the semiconductor CMOS devices. We have investigated very thin$ SiO_2$ gate oxide layers and found anomaly between the thickness determined with capacitance measurement and these obtained with cross-sectional high resolution transmission electron microscopy. The thicknesses difference of the two becomes important for the thickness of the oxide below 5nm. We propose that the variation of dielectric constant in thin oxide films cause the anomaly. We modeled the behavior as (equation omitted) and determined $\varepsilon_{bulk}$=3.9 and $\varepsilon_{int}$=-4.0. We predict that optimum $SiO_2$ gate oxide thickness may be $20\AA$ due to negative contribution of the interface dielectric constant. These new results have very important implication for designing the CMOS devices.s.

• JSTS:Journal of Semiconductor Technology and Science
• /
• 제1권1호
• /
• pp.31-39
• /
• 2001

W polymetal gate technology for giga bit DRAM are presented. Key module processes for polymetal gate are studied in detail. $W/WN_x/poly-silicon$ adopted for a word line of 256Mbit DRAM has good gate oxide integrity and junction leakage characteristics through full integration, which is comparable to those of conventional $WSi_x$/Poly-silicon gate process. These results undoubtedly show that $W/WN_x/poly-silicon$ is the strongest candidate as a word line for Giga bit DRAM.

• 진공이야기
• /
• 제5권2호
• /
• pp.18-22
• /
• 2018

wo dimensional (2D) van der Waals (vdW) nanosheet semiconductors have recently attracted much attention from researchers because of their potentials as active device materials toward future nano-electronics and -optoelectronics. This review mainly focuses on the features and applications of state-of-the-art vdW 2D material devices which use transition metal dichalcogenides, graphene, hexagonal boron nitride (h-BN), and black phosphorous: field effect transistors (FETs), complementary metal oxide semiconductor (CMOS) inverters, Schottky diode, and PN diode. In a closing remark, important remaining issues of 2D vdW devices are also introduced as requests for future electronics and photonics applications.

• 한국전기전자재료학회:학술대회논문집
• /
• 한국전기전자재료학회 2007년도 추계학술대회 논문집
• /
• pp.94-95
• /
• 2007

In this paper, the dependence of electrical characteristics of Silicon-$Al_2O_3$-Nitride-Oxide-Silicon (SANOS) memory cell transistors and program speed, reliability of memory device on interface trap between Si substrate and tunneling oxide was investigated. The devices were fabricated by the identical processing in a single lot except the deposition method of the charge trapping layer, nitride. In the case of P/E speed, it was shown that P/E speed is slower in the SONOS cell transistors with larger interface trap density by charge blocking effect, which is confirmed by simulation results. However, the data retention characteristics show much less dependence on interface trap. Therefore, to improve SANOS memory characteristic, it is very important to optimize the interface trap and charge trapping layer.

• 한국재료학회지
• /
• 제2권3호
• /
• pp.228-238
• /
• 1992

서브마이크론 설계규칙을 갖는 소자의 이층 배선 공정에서 다챔버 장비를 이용한 금속 층간절연막의 공극없는 평탄화를 위하여 PECVD와 $O_3$ ThCVD산화막의 증착시 층덮힘성을 연구하였다. 산화막의 두께가 증가됨에 따라 변화되는 순간단차비의 개념을 도입하여 공극형성의 개시점을 예측할 수 있는 관계식을 모델링하였고, 금속배선간격의 초기 단차비가 다양한 패턴에서 산화막의 두께에 따른 순간 단차비의 변화를 조사하였다. 모델링 검정결과 $5^{\circ}$이하의 re-entrant각을 갖는 TEOS에 의한 PECVO 산화막의 순간단차비가 모델링에 잘 일치하였다. 공극없는 평탄화는 제1층의 PECVD 산화막의 순간 단차비를 0.8이하로 유지하거나 Ar sputter식각을 통하여 산화막의 모서리에 경사를 준후 층덮힘성이 우수한 $O_3$ ThCVD산화막을 증착함으로써 가능하였다. $O_3$ ThCVD산화막의 etchback이 non etchback공정에 비하여 via접쪽저항체인에서 높은 수율을 보였으며, via접촉저항은 $0.1~0.3{\Omega}/{\mu}m^2$로 나타났다.

• 한국전기전자재료학회:학술대회논문집
• /
• 한국전기전자재료학회 1998년도 춘계학술대회 논문집
• /
• pp.79-82
• /
• 1998

Film characteristics of thin ONO dielectric layers for MONOS(metal-oxide-nitride-oxide-semiconductor) EEPRM was investigated by AES and AFM. Second derivative spectra of AES Si LVV overlapping peak provided useful information for chemical state analysis of superthin film. The ONO films with dimension of tunneling oxide 24${\AA}$, nitride 33${\AA}$, and blocking oxide 40${\AA}$ were fabricated. During deposition of the LPCVD nitride films on tunneling oxide, this thin oxide was nitrized. When the blocking oxide were deposited on the nitride film, the oxygen not only oxidized the nitride surface, but diffused through the nitride. The results of ONO film analysis exhibits that it is made up of SiO$_2$(blocking oxide)/O-rich SiON(interface/N-rich SiON(nitride)/-rich SiON(interface)/N-rich SiON(nitride)/O-rich SiON(tunneling oxide).

• 한국정보통신학회논문지
• /
• 제7권2호
• /
• pp.269-275
• /
• 2003

저전압 프로그래밍이 가능한 플래시메모리를 실현하기 위하여 0.35$\mu\textrm{m}$ CMOS 공정 기술을 이용하여 터널링산화막, 질화막 그리고 블로킹산화막의 두께가 각각 2.4nm, 4.0nm, 2.5nm인 SONOS 트랜지스터를 제작하였으며, SONOS 메모리 셀의 면적은 1.32$\mu$$m^2$이었다. 질화막의 두께를 스케일링한 결과, 10V의 동작 전압에서 소거상태로부터 프로그램상태로, 반대로 프로그램상태에서 소거상태로 스위칭 하는데 50ms의 시간이 필요하였으며, 최대 메모리윈도우는 1.76V이었다. 그리고 질화막의 두께를 스케일링함에도 불구하고 10년 후에도 0.5V의 메모리 윈도우를 유지하였으며, 105회 이상의 프로그램/소거 반복동작이 가능함을 확인하였다. 마지막으로 부유게이트 소자에서 심각하게 발생하고있는 과도소거현상이 SONOS 소자에서는 나타나지 않았다.