• 한국전기전자재료학회논문지
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• 제13권9호
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• pp.729-734
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• 2000

Recently, Very Large Scale Integrated (VLSI) circuit & deep-submicron bulk Complementary Metal Oxide Semiconductor(CMOS) devices require gate electrode materials such as metal-silicide, Titanium-silicide for gate oxides. Many previous authors have researched the improvement sub-micron gate oxide quality. However, few have reported on the electrical quality and reliability on the ultra thin gate oxide. In this paper, at first, I recommand a novel shallow trench isolation structure to suppress the corner metal-oxide semiconductor field-effect transistor(MOSFET) inherent to shallow trench isolation for sub 0.1${\mu}{\textrm}{m}$ gate oxide. Different from using normal LOCOS technology deep-submicron CMOS devices using novel Shallow Trench Isolation(STI) technology have a unique"inverse narrow-channel effects"-when the channel width of the devices is scaled down, their threshold voltage is shrunk instead of increased as for the contribution of the channel edge current to the total channel current as the channel width is reduced. Secondly, Titanium silicide process clarified that fluorine contamination caused by the gate sidewall etching inhibits the silicidation reaction and accelerates agglomeration. To overcome these problems, a novel Two-step Deposited silicide(TDS) process has been developed. The key point of this process is the deposition and subsequent removal of titanium before silicidation. Based on the research, It is found that novel STI structure by the SEM, in addition to thermally stable silicide process was achieved. We also obtained the decrease threshold voltage value of the channel edge. resulting in the better improvement of the narrow channel effect. low sheet resistance and stress, and high threshold voltage. Besides, sheet resistance and stress value, rms(root mean square) by AFM were observed. On the electrical characteristics, low leakage current and trap density at the Si/SiO$_2$were confirmed by the high threshold voltage sub 0.1${\mu}{\textrm}{m}$ gate oxide.

• 한국전기전자재료학회논문지
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• 제11권10호
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• pp.778-783
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• 1998

Film characteristics of thin ONO dielectric layers for MONOS(metal-oxide-nitride-oxide-semiconductor) EEPROM was investigated by TEM, AES and AFM. Seocnd derivative spectra of Auger Si LVV overlapping peak provide useful information fot chemical state analysis of superthin film. The ONO film with dimension of tunnel oxide 23$\AA$, nitride 33$\AA$, and blocking oxide 40$\AA$ was fabricated. During deposition of the LPCVD nitride film on tunnel oxide, this thin oxide was nitrized. When the blocking oxide was deposited on the nitride film, the oxygen not only oxidized the nitride surface, but diffused through the nitride. The results of ONO film analysis exhibits that it is made up of $SiO_2$ (blocking oxide)/O-rich SiON(interface)/N-rich SiON(nitride)/ O-rich SiON(tunnel oxide)

• 한국재료학회지
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• 제2권4호
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• pp.285-292
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• 1992

Si(100) 웨이퍼를 사용하여 RTP 장비에서 $O_2$와 $N_2$O 분위기에서 8nm의 oxynitride를 제조 하였다. 기존의 로(furnace) 열산화막과 비교해서 oxynitride는 I-V, TDDB 특성이 우수하였고, flat-band voltage shift도 적었으며 $BF_2이온$ 주입에 의한 붕소 투과 억제 특성도 우수하다. 유전상수는 oxynitride가 열산화막에 비해서 크다. Oxynitride는 순수한 Si$O_2$유사하게 V 〉${\varphi}_0$ 구간에서 Fowler-Nordheim 터널링 특성을 나타낸다. SIMS, AES, 그리고 XPS 분석 결과 질소 pile-up이 Si$O_2$/Si 계면에서 나타나고, 이것은 oxynitride 산화막 특성 향상과 깊은 관련이 있다.

• Transactions on Electrical and Electronic Materials
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• 제18권1호
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• pp.55-57
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• 2017

Amorphous oxide thin film transistors (TFTs) were fabricated with 0.5 wt% silicon doped zinc tin oxide (a-0.5SZTO) thin film deposited by radio frequency (RF) magnetron sputtering. In order to investigate the effect of annealing treatment on the electrical properties of TFTs, a-0.5SZTO thin films were annealed at three different temperatures ($300^{\circ}C$, $500^{\circ}C$, and $700^{\circ}C$ for 2 hours in a air atmosphere. The structural and electrical properties of a-0.5SZTO TFTs were measured using X-ray diffraction and a semiconductor analyzer. As annealing temperature increased from $300^{\circ}C$ to $500^{\circ}C$, no peak was observed. This provided crystalline properties indicating that the amorphous phase was observed up to $500^{\circ}C$. The electrical properties of a-0.5SZTO TFTs, such as the field effect mobility (${\mu}_{FE}$) of $24.31cm^2/Vs$, on current ($I_{ON}$) of $2.38{\times}10^{-4}A$, and subthreshold swing (S.S) of 0.59 V/decade improved with the thermal annealing treatment. This improvement was mainly due to the increased carrier concentration and decreased structural defects by rearranged atoms. However, when a-0.5SZTO TFTs were annealed at $700^{\circ}C$, a crystalline peak was observed. As a result, electrical properties degraded. ${\mu}_{FE}$ was $0.06cm^2/Vs$, $I_{ON}$ was $5.27{\times}10^{-7}A$, and S.S was 2.09 V/decade. This degradation of electrical properties was mainly due to increased interfacial and bulk trap densities of forming grain boundaries caused by the annealing treatment.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2012년도 제42회 동계 정기 학술대회 초록집
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• pp.341-341
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• 2012

Recently, oxide semi-conductor materials have been investigated as promising candidates replacing a-Si:H and poly-Si semiconductor because they have some advantages of a room-temperature process, low-cost, high performance and various applications in flexible and transparent electronics. Particularly, amorphous indium-gallium-zinc-oxide (a-IGZO) is an interesting semiconductor material for use in flexible thin film transistor (TFT) fabrication due to the high carrier mobility and low deposition temperatures. In this work, we demonstrated improvement of flexibility in IGZO TFTs, which were fabricated on polyimide (PI) substrate. At first, a thin poly-4vinyl phenol (PVP) layer was spin coated on PI substrate for making a smooth surface up to 0.3 nm, which was required to form high quality active layer. Then, Ni gate electrode of 100 nm was deposited on the bare PVP layer by e-beam evaporator using a shadow mask. The PVP and $Al_2O_3$ layers with different thicknesses were used for organic/inorganic multi gate dielectric, which were formed by spin coater and atomic layer deposition (ALD), respectively, at $200^{\circ}C$. 70 nm IGZO semiconductor layer and 70 nm Al source/drain electrodes were respectively deposited by RF magnetron sputter and thermal evaporator using shadow masks. Then, IGZO layer was annealed on a hotplate at $200^{\circ}C$ for 1 hour. Standard electrical characteristics of transistors were measured by a semiconductor parameter analyzer at room temperature in the dark and performance of devices then was also evaluated under static and dynamic mechanical deformation. The IGZO TFTs incorporating hybrid gate dielectrics showed a high flexibility compared to the device with single structural gate dielectrics. The effects of mechanical deformation on the TFT characteristics will be discussed in detail.

• 한국재료학회지
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• 제20권8호
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• pp.401-407
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• 2010

We studied the influence of different types of metal electrodes on the performance of solution-processed zinc tin oxide (ZTO) thin-film transistors. The ZTO thin-film was obtained by spin-coating the sol-gel solution made from zinc acetate and tin acetate dissolved in 2-methoxyethanol. Various metals, Al, Au, Ag and Cu, were used to make contacts with the solution-deposited ZTO layers by selective deposition through a metal shadow mask. Contact resistance between the metal electrode and the semiconductor was obtained by a transmission line method (TLM). The device based on an Al electrode exhibited superior performance as compared to those based on other metals. Kelvin probe force microscopy (KPFM) allowed us to measure the work function of the oxide semiconductor to understand the variation of the device performance as a function of the types metal electrode. The solution-processed ZTO contained nanopores that resulted from the burnout of the organic species during the annealing. This different surface structure associated with the solution-processed ZTO gave a rise to a different work function value as compared to the vacuum-deposited counterpart. More oxygen could be adsorbed on the nanoporous solution-processed ZTO with large accessible surface areas, which increased its work function. This observation explained why the solution-processed ZTO makes an ohmic contact with the Al electrode.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2016년도 제50회 동계 정기학술대회 초록집
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• pp.390.2-390.2
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• 2016

Single crystalline indium-tin-oxide (ITO) nanowires (NWs) were grown by sputtering method. A thin Ni film of 5 nm was coated before ITO sputtering. Thermal treatment forms Ni nanoparticles, which act as templates to diffuse Ni into the sputtered ITO layer to grow single crystalline ITO NWs. Highly optical transparent photoelectric devices were realized by using a transparent metal-oxide semiconductor heterojunction by combining of p-type NiO and n-type ZnO. A functional template of ITO nanowires was applied to this transparent heterojunction device to enlarge the light-reactive surface. The ITO NWs/n-ZnO/p-NiO heterojunction device provided a significant high rectification ratio of 275 with a considerably low reverse saturation current of 0.2 nA. The optical transparency was about 80% for visible wavelengths, however showed an excellent blocking UV light. The nanostructured transparent heterojunction devices were applied for UV photodetectors to show ultra fast photoresponses with a rise time of 8.3 mS and a fall time of 20 ms, respectively. We suggest this transparent and super-performing UV responser can practically applied in transparent electronics and smart window applications.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2015년도 제49회 하계 정기학술대회 초록집
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• pp.207.1-207.1
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• 2015

차세대 디스플레이 소자로서 TAOS TFT (transparent amorphous oxide semiconductor Thin Film Transistor)가 주목 받고 있다. 또한, 최근에는 값 비싼 전자 제품을 저렴하고 간단히 처분 할 수 있는 시스템으로 대신 하는 연구가 진행되고 있다. 그중, cellulose-fiber에 전기적 시스템을 포함시키는 e-paper에 대한 관심이 활발하다. cellulose fiber는 가볍고 깨지지 않으며 휘는 성질을 가지고 있다. 가격도 저렴하고 가공이 용이하여 차세대 기판의 재료로서 주목받고 있다. 하지만, cellulose-fiber 위에는 고온의 열처리공정과 고품질 박막 성장이 어려워서 TFT 제작에 어려움을 겪고 있다. 이러한 문제를 해결하기 위해서 산화물 반도체를 이용하여 TFT를 제작한 사례가 보고되고 있다. 또한, 채널 물질 뿐만 아니라 cellulose fiber에도 다른 물질을 첨가하거나 증착하여 전기적 화학적 특성을 개선시킨 사례도 많이 보고되고 있다. 본 연구에서는 가장 저품질의 용지로 알려진 신문지와 A4용지를 gate dielectric을 이용하여서 a-IGZO TFT를 제작하였다. 하지만, cellulose fiber로 만들어진 TFT의 경우에는 고온의 열처리가 불가능 하다. 따라서 저온에서 높을 효율은 보이는 microwave energy를 이용하여 열처리를 진행하였다. 추가적으로 저품질의 종이의 특성을 개선시키기 위해서 high-k metal-oxide solution precursor를 첨가 하여 TFT의 특성을 개선시켰다. 결과적으로 cellulose fiber에 metal-oxide solution precursor을 첨가하는 공정과 micro wave를 조사하는 방법을 사용하여 100도 이하에서 cellulose fiber를 저렴하고 우수한 성능의 TFT를 제작에 성공하였다.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2008년도 추계학술대회 논문집 Vol.21
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• pp.159-159
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• 2008

투명전도체 (transparent conducting oxides: TCOs) 는 일반적으로 $10^3\Omega^{-1}Cm^{-1}$의 전도도, 가시광 영역에서 80%이상의 투명성을 가지는 재료로서, 액정 박막 표시 장치(TFT-LCD), 광기전성 소자, 유기 발광 소자, 에너지 절약 창문, 태양전지(sollar cell) 등 전극으로 사용되고 있다. 최근에는 TCO의 전도도특성을 조절하여 반도성특성을 가진 투명 산화물 반도체(transparent oxide semiconductor: TOS) 을 이용한 박막 트랜지스터 연구가 활발히 진행 중이다. 기존의 실리콘을 기반으로 하는 박막 트랜지스터의 낮은 이동도, 불투명성의 특성을 가지고 있지만, 산화물 박막트랜지스터는 높은 이동도를 발현 할 수 있을 뿐만 아니라, 넓은 밴드갭 에너지를 갖는 산화물을 이용하므로 투명한 특성도 발현 할 수 있어 차세대 디스플레이의 구동소자로서 응용연구가 되고 있다. 이에 본 연구에서는 박막트랜지스터 channel layer로서의 Indium-Tin-Zinc oxide 적용특성을 조사하였다. Indium, Tin, Zinc 의 혼합비율을 다양하게 조절하여 타겟을 제작하였다. 이를 RF magnetron sputtering 를 이용하여 박막으로 성장시켰으며, 기판으로는 glass 기판을 사용하였다. 박막 성장시 아르곤과 산소의 비율을 다양하게 조절하였다. 성장시킨 박막은 Hall effect, Transmittance, Work function, XRD등을 이용하여 전기적, 광학적, 구조특성을 평가하였다. Indium-Tin-Zinc Oxide(ITZO) 을 channel layer로 사용하여 Thin-film transistor 을 제작하여, TFT의 I-V 및 stability특성을 평가하였다.

• 한국전기전자재료학회논문지
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• 제13권10호
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• pp.822-827
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• 2000

The Si-SiO$_2$interface trap and nitride bulk trap distribution of SONOSFET(polysilicon-oxide-nitride-oxide-semiconductor field effect transistor) NVSM (nonvolatile semiconductor memory) cell is investigated by single junction charge pumping method. The device was fabricated by 0.35㎛ standard logic fabrication process including the ONO stack dielectrics. The thickness of ONO dielectricis are 24$\AA$ for tunnel oxide, 74 $\AA$ for nitride and 25 $\AA$ for blocking oxide, respectively. By the use of single junction charge pumping method, the lateral profiles of both interface and memory traps can be calculated directly from experimental charge pumping results without complex numerical simulation. The interface traps were almost uniformly distributed over the whole channel region and its maximum value was 7.97$\times$10$\^$10/㎠. The memory traps were uniformly distributed in the nitride layer and its maximum value was 1.04$\times$10$\^$19/㎤. The degradation characteristics of SONOSFET with write/erase cycling also were investigated.