• Proceedings of the Korean Vacuum Society Conference
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• 2014.02a
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• pp.346.2-346.2
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• 2014

To use the GaN based light-emitting diodes (LEDs) as solid state lighting sources, the improvement of light extraction and internal quantum efficiency is essential factors for high brightness LEDs. In this study, we suggested the new materials system of a zinc tin oxide (ZTO) layer formed on blue LED epi-structures to improve the light extraction. ZTO is a representative n-type oxide material consisted of ZnO and SnO system. Moreover, ZTO is one of the promising oxide semiconductor material. Even though ZTO has higher chemical stability than IGZO owing to its SnO2 content this has high mobility and high reliability. After formation of ZTO layer on p-GaN layer by using the spin coating method, structural and optical properties are investigated. The x-ray diffraction (XRD) measurement results show the successful formation of ZTO. The photoluminescence (PL) and absorption spectrum shows that it has 3.6-4.1eV band gap. Finally, the light extraction properties of ZTO/LED chip using electroluminescence (EL) measurement were investigated. The experimental and theoretical analyses were simultaneously conducted.

• 한국정보디스플레이학회:학술대회논문집
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• 2009.10a
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• pp.1582-1585
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• 2009

The effects of bias stress on spin-coated zinc tin oxide (ZTO) transistors are investigated. Applying a positive bias stress results in the displacement of the transfer curves in the positive direction without changing the field effect mobility or the subthreshold behavior. Device instability appears to be a consequence of the charging and discharging of temporal trap states at the interface and in the zinc tin oxide channel region.

• Proceedings of the Materials Research Society of Korea Conference
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• 2009.05a
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• pp.52.1-52.1
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• 2009

Cupric oxide (CuO) is a p-type semiconductor with band gap of ~1.7 eV and reported to be suitable for catalysis, lithium-copper oxide electrochemical cells, and gas sensors applications. The nanoparticles, plates and nanowires of CuO were found sensing to NO2, H2S and CO. In this work, we report about the comparison about hydrogen sensing of nano thin film and nanowires structured CuO deposited on single-walled carbon nanotubes (SWNTs). The thin film and nanowires are synthesized by deposition of Cu on different substrate followed by oxidation process. Nano thin films of CuO are deposited on thermally oxidized silicon substrate, whereas nanowires are synthesized by using a porous thin film of SWNTs as substrate. The hydrogen sensing properties of synthesized materials are investigated. The results showed that nanowires cupric oxide deposited on SWNTs showed higher sensitivity to hydrogen than those of nano thin film CuO did.

• Journal of the Korean institute of surface engineering
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• v.33 no.4
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• pp.217-221
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• 2000

The gate oxide thickness is becoming thinner and thinner in order to speed up the semiconductor CMOS devices. We have investigated very thin$ SiO_2$ gate oxide layers and found anomaly between the thickness determined with capacitance measurement and these obtained with cross-sectional high resolution transmission electron microscopy. The thicknesses difference of the two becomes important for the thickness of the oxide below 5nm. We propose that the variation of dielectric constant in thin oxide films cause the anomaly. We modeled the behavior as (equation omitted) and determined $\varepsilon_{bulk}$=3.9 and $\varepsilon_{int}$=-4.0. We predict that optimum $SiO_2$ gate oxide thickness may be $20\AA$ due to negative contribution of the interface dielectric constant. These new results have very important implication for designing the CMOS devices.s.

• JSTS:Journal of Semiconductor Technology and Science
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• v.1 no.1
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• pp.31-39
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• 2001

W polymetal gate technology for giga bit DRAM are presented. Key module processes for polymetal gate are studied in detail. $W/WN_x/poly-silicon$ adopted for a word line of 256Mbit DRAM has good gate oxide integrity and junction leakage characteristics through full integration, which is comparable to those of conventional $WSi_x$/Poly-silicon gate process. These results undoubtedly show that $W/WN_x/poly-silicon$ is the strongest candidate as a word line for Giga bit DRAM.

• Vacuum Magazine
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• v.5 no.2
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• pp.18-22
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• 2018

wo dimensional (2D) van der Waals (vdW) nanosheet semiconductors have recently attracted much attention from researchers because of their potentials as active device materials toward future nano-electronics and -optoelectronics. This review mainly focuses on the features and applications of state-of-the-art vdW 2D material devices which use transition metal dichalcogenides, graphene, hexagonal boron nitride (h-BN), and black phosphorous: field effect transistors (FETs), complementary metal oxide semiconductor (CMOS) inverters, Schottky diode, and PN diode. In a closing remark, important remaining issues of 2D vdW devices are also introduced as requests for future electronics and photonics applications.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2007.11a
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• pp.94-95
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• 2007

In this paper, the dependence of electrical characteristics of Silicon-$Al_2O_3$-Nitride-Oxide-Silicon (SANOS) memory cell transistors and program speed, reliability of memory device on interface trap between Si substrate and tunneling oxide was investigated. The devices were fabricated by the identical processing in a single lot except the deposition method of the charge trapping layer, nitride. In the case of P/E speed, it was shown that P/E speed is slower in the SONOS cell transistors with larger interface trap density by charge blocking effect, which is confirmed by simulation results. However, the data retention characteristics show much less dependence on interface trap. Therefore, to improve SANOS memory characteristic, it is very important to optimize the interface trap and charge trapping layer.

• Korean Journal of Materials Research
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• v.2 no.3
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• pp.228-238
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• 1992

An investigation on the step-coverage of PECVD and $O_3$ ThCVD oxides was undertaken to implement into the void-free inter metal dielectric planarization using multi-chamber system for the submicron double level metallization. At various initial aspect ratios the instantaneous aspect ratios were measured through modelling and experiment by depositing the oxides up to $0.9{\mu}m$ in thickness in order to monitor the onset of void formation. The modelling was found to be in a good agreement with the observed instantaneous aspect ratio of TEOS-based PECVD oxide whose re-entrant angle was less than $5^{\circ}$. It is demonstrated that either keeping the instantaneous aspect ratio of PECVD oxide as a first layer less than a factor of 0.8 or employing Ar sputter etch to create sloped oxide edge ensures the void-free planarization after$O_3$ ThCVD oxide deposition whose step-coverage is superior to PECVD oxide. It has been observed that $O_3$ ThCVD oxide etchback scheme has shown higher yield of via contact chain than non etchback process, with resistance per via contact of $0.1~0.3{\Omega}/{\mu}m^2$.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1998.06a
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• pp.79-82
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• 1998

Film characteristics of thin ONO dielectric layers for MONOS(metal-oxide-nitride-oxide-semiconductor) EEPRM was investigated by AES and AFM. Second derivative spectra of AES Si LVV overlapping peak provided useful information for chemical state analysis of superthin film. The ONO films with dimension of tunneling oxide 24${\AA}$, nitride 33${\AA}$, and blocking oxide 40${\AA}$ were fabricated. During deposition of the LPCVD nitride films on tunneling oxide, this thin oxide was nitrized. When the blocking oxide were deposited on the nitride film, the oxygen not only oxidized the nitride surface, but diffused through the nitride. The results of ONO film analysis exhibits that it is made up of SiO$_2$(blocking oxide)/O-rich SiON(interface/N-rich SiON(nitride)/-rich SiON(interface)/N-rich SiON(nitride)/O-rich SiON(tunneling oxide).

• Journal of the Korea Institute of Information and Communication Engineering
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• v.7 no.2
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• pp.269-275
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• 2003

Polysilicon-oxide-nitride-oxide-silicon(SONOS) transistors were fabricated by using 0.35${\mu}{\textrm}{m}$ complementary metal-oxide-semiconductor(CMOS) process technology to realize a low voltage programmable flash memory. The thickness of the tunnel oxide, the nitride, and the blocking oxide were 2.4nm, 4.0nm, and 2.5nm, respectively, and the cell area of the SONOS memory was 1.32$\mu$$m^2$. The SONOS device revealed a maximum memory window of 1.76V with a switching time of 50ms at 10V programming, as a result of the scaling effect of the nitride. In spite of scaling of nitride thickness, memory window of 0.5V was maintained at the end of 10 years, and the endurance level was at least 105 program/erase cycles. Over-erase, which was shown seriously in floating gate device, was not shown in SONOS device.