• Title/Summary/Keyword: Oxide Semiconductor

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Cu Ions Removal Using Graphene Oxide and in-situ Spectroscopic Monitoring Method of Residual Cu Ions (산화 그래핀을 이용한 구리이온 흡착과 투과도 특성을 이용한 구리이온 농도 실시간 측정)

  • Kim, Seungdu;Ryou, Heejoong;Oh, Hoon-Jung;Hwang, Wan Sik
    • Journal of the Semiconductor & Display Technology
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    • v.20 no.2
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    • pp.87-91
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    • 2021
  • Various Cu ions are discharged into water from various industries, which results in a severe trouble for groundwater, soil, air, and eventually animals and humans. In this work, graphene oxide (GO) is introduced as a Cu removal absorber and the real-time monitoring method is demonstrated. The results show that GO is a very effective material to absorb Cu ions in the solution. In addition, the residual Cu ions in the solution is monitored via optical transmittance method, which well match with Inductively Coupled Plasma Mass Spectrometer (ICP-MS) analysis.

Morphological and Electrical Characteristics of nc-ZnO/ZnO Thin Films Fabricated by Spray-pyrolysis for Field-effect Transistor Application (전계효과트랜지스터 기반 반도체 소자 응용을 위한 스프레이 공정을 이용한 nc-ZnO/ZnO 박막 제작 및 특성 분석)

  • Cho, Junhee
    • Journal of the Semiconductor & Display Technology
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    • v.20 no.4
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    • pp.1-5
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    • 2021
  • Field-effect transistors based on solution-processed metal oxide semiconductors has attracted huge attention due to their intrinsic characteristics of optical and electrical characteristics with benefits of simple and low-cost process. Especially, spray-pyrolysis has shown excellent device performance which compatible to vacuum-processed Field-effect transistors. However, the high annealing temperature for crystallization of MOS and narrow range of precursors has impeded the progress of the technology. Here, we demonstrated the nc-ZnO/ZnO films performed by spray-pyrolysis with incorporating ZnO nanoparticles into typical ZnO precursor. The films exhibit preserving morphological properties of poly-crystalline ZnO and enhanced electrical characteristics with potential for low-temperature processability. The influence of nanoparticles within the film was also researched for realizing ZnO films providing good quality of performance.

$Cu_2O$ p-type oxide-semiconductor film ($Cu_2O$ p-형 산화물반도체 박막)

  • Song, Byeong-Jun;Lee, Ho-Nyeon
    • Proceedings of the KAIS Fall Conference
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    • 2010.11a
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    • pp.356-358
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    • 2010
  • Cuprous oxide ($Cu_2O$)를 기초로 하여 산화 박막 트랜지스터에 대하여 연구를 하였다. 일정한 두께의 cuprous oxide ($Cu_2O$) 박막을 조건별로 열처리 공정을 하고 그에 따른 변화를 측정을 하였다. 그 측정한 결과 중 가장 좋은 열처리 조건으로 열 증착 방식(Vacuum Thermal Evaporation)을 사용하여 cuprous oxide ($Cu_2O$) 비정질 산화 박막 트랜지스터를 제작 및 측정했다.

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Electrical Characteristics of Thin SiO$_2$Layer

  • Hong, Nung-Pyo;Hong, Jin-Woong
    • KIEE International Transactions on Electrophysics and Applications
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    • v.3C no.2
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    • pp.55-58
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    • 2003
  • This paper examines the electrical characteristic of single oxide layer due to various diffusion conditions, substrate orientations, substrate resistivity and gas atmosphere in a diffusion furnace. The oxide quality was examined through the capacitance-voltage characteristic due to the annealing time after oxidation process, and the capacitance-voltage characteristics of the single oxide layer by will be described via semiconductor device simulation.

Study of Improvement of Gate Oxide Quality by Using an Advanced, $TiSi_2$ process & STI (새로운 $TiSi_2$ 형성방법과 STI를 이용한 초박막 게이트 산화막의 특성 개선 연구)

  • 엄금용;오환술
    • Proceedings of the IEEK Conference
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    • 2000.11b
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    • pp.41-44
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    • 2000
  • Ultra large scale integrated circuit(ULSI) & complementary metal oxide semiconductor(CMOS) circuits require gate electrode materials such as meta] silicides, titanium-silicide for gate oxides. Many previous authors have researched the improvements sub-micron gate oxide quality. However, little has been done on the electrical quality and reliability of ultra thin gates. In this research, we recommend novel shallow trench isolation structure and two step TiSi$_{2}$ formation for sub 0.1${\mu}{\textrm}{m}$ gate oxide.

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Electrochemical Fabrication of CdS/CO Nanowrite Arrays in Porous Aluminum Oxide Templates

  • Yoon, Cheon-Ho;Suh, Jung-Sang
    • Bulletin of the Korean Chemical Society
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    • v.23 no.11
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    • pp.1519-1523
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    • 2002
  • A procedure for preparing semiconductor/metal nanowire arrays is described, based on a template method which entails electrochemical deposition into nanometer-wide parallel pores of anodic aluminum oxide films on aluminum. Aligned CdS/Co heterostructured nanowires have been prepared by ac electrodeposition in the anodic aluminum oxide templates. By varying the preparation conditions, a variety of CdS/Co nanowire arrays were fabricated, whose dimensional properties could be adjusted.

Direct Writing of Semiconducting Oxide Layer Using Ink-Jet Printing

  • Lee, Sul;Jeong, Young-Min;Moon, Joo-Ho
    • 한국정보디스플레이학회:학술대회논문집
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    • 2007.08a
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    • pp.875-877
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    • 2007
  • Zinc tin oxide (ZTO) sol-gel solution was synthesized for ink-jet printable semiconducting ink. Bottom-contact type TFT was produced by printing the ZTO layer between the source and drain electrodes. The transistor involving the ink-jet printed ZTO had the $mobility\;{\sim}\;0.01\;cm^2V^{-1}s^{-1}$. We demonstrated the direct-writing of semiconducting oxide for solution processed TFT fabrication.

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A Study on the TDDB Characteristics of Superthin ONO structure (초박막 GNO 구조의 TDDB 특성에 관한 연구)

  • 국삼경;윤성필;이상은;김선주;서광열
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 1997.11a
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    • pp.25-29
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    • 1997
  • Capacitor-type MONOS (metal-oxide-nitride-oxide- semiconductor) NVSMs with 23$\AA$ tunneling oxide and 40$\AA$ blocking oxide were fabricated. The thicknesses of nitride layer were 45$\AA$, 91$\AA$ and 223$\AA$, Breakdown characteristics of MONOS devices were measured to investigate the reliability of superthin ONO structure using ramp voltage and constant voltage method. Reducing the nitride thickness will significantly increase the reliablity of MONOS NVSM.

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MOS Capacitor 에서 Fixed Oxide Charge 가 문턱전압에 미치는 영향 분석

  • Cha, Su-Hyeong
    • Proceeding of EDISON Challenge
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    • 2016.03a
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    • pp.362-364
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    • 2016
  • 본 논문에서는 MOS(Metal Oxide Semiconductor) Capacitor의 산화막내에 다양한 원인에 의해 존재하는 비이상적인 전하들 중 Fixed Oxide Charge가 소자의 문턱전압에 어떤 영향을 주는지 분석했다. 분석한 결과 n+ polysilicon Gate를 가지고, 산화막인 $SiO_2$의 두께가 3nm이고, 도핑농도가 $10^{18}cm^{-2}$인 P형 실리콘 기판으로 이루어진 MOS Capacitor에서 Fixed Oxide Charge Density가 $C/cm^2$ 이상일 때 문턱전압을 0.01V 이상 감소시키고 $C/cm^2$ 이하일 때 문턱전압을 0.01V 이상 증가시켰다.

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