• Journal of IKEEE
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• v.19 no.1
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• pp.41-44
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• 2015

Silicon trench process for bulk fin field effect transistor (finFET) is suggested without using chemical mechanical polishing (CMP) that cause contamination problems with chemical stuff. This process uses thickness difference of photo resistor spin coating and silicon nitride sacrificial layer. Planarization of silicon oxide and silicon trench formation can be performed with etching processes. In this work 50 nm silicon trench is fabricated with AZ 1512 photo resistor and process results are introduced.

• Journal of the Korean Society for Precision Engineering
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• v.32 no.1
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• pp.69-74
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• 2015

Cadmium telluride (CdTe) is being developed for thin film of the X-Ray detector recently. But a rough surface of the CdTe should be improved for resolution and signal speed. This paper shows the study on the improvement of surface roughness and removal rate by applying Chemical Mechanical Polishing. The conventional potassium hydroxide (KOH) based colloidal silica slurry could not realize a mirror surface without physical defects, resulting in low material removal rate and many scratches on surface. In order to enhance chemical reaction such as form oxidized layer on the surface of cadmium telluride, we used hydrogen peroxide ($H_2O_2$) as an oxidizer. Consequently, in case of 3 wt% concentration of hydrogen peroxide, the highest MRR (938 nm/min) and the lowest surface roughness ($R_{p-v}=10.69nm$, $R_a=0.8nm$) could be obtained. EDS was also used to confirm the generated oxide of cadmium telluride surface.

• Journal of the Microelectronics and Packaging Society
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• v.19 no.2
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• pp.29-33
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• 2012

The demand for 3D wafer level integration has been increasing significantly. Although many technical challenges of wafer stacking are still remaining, wafer stacking is a key technology for 3D integration due to a high volume manufacturing, smaller package size, low cost, and no need for known good die. Among several new process techniques Cu-to-Cu wafer bonding is the key process to be optimized for the high density and high performance IC manufacturing. In this study two main challenges for Cu-to-Cu wafer bonding were evaluated: misalignment and bond quality of bonded wafers. It is demonstrated that the misalignment in a bonded wafer was mainly due to a physical movement of spacer removal step and the bond quality was significantly dependent on Cu bump dishing and oxide erosion by Cu CMP.

• Proceedings of the Korean Vacuum Society Conference
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• 2011.02a
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• pp.68-68
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• 2011

As feature size is smaller, new technology are needed in semiconductor factory such as gap-fill technology for sub 100nm, development of ALD equipment for Cu barrier/seed, oxide trench etcher technology for 25 nm and beyond, development of high throughput Cu CMP equipment for 30nm and development of poly etcher for 25 nm and so on. We are focus on gap-fill technology for sub-30nm. There are many problems, which are leaning, over-hang, void, micro-pore, delaminate, thickness limitation, squeeze-in, squeeze-out and thinning phenomenon in sub-30 nm gap fill. New gap-fill processes, which are viscous oxide-SOD (spin on dielectric), O3-TEOS, NF3 Based HDP and Flowable oxide have been attempting to overcome these problems. Some groups investigated SOD process. Because gap-fill performance of SOD is best and process parameter is simple. Nevertheless these advantages, SOD processes have some problems. First, material cost is high. Second, density of SOD is too low. Therefore annealing and curing process certainly necessary to get hard density film. On the other hand, film density by Flowable oxide process is higher than film density by SOD process. Therefore, we are focus on Flowable oxide. In this work, dielectric film were deposited by PECVD with TSA(Trisilylamine - N(SiH3)3) and NH3. To get flow-ability, the effect of plasma treatment was investigated as function of O2 plasma power. QMS (quadruple mass spectrometry) and FTIR was used to analysis mechanism. Gap-filling performance and flow ability was confirmed by various patterns.

• Transactions on Electrical and Electronic Materials
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• v.7 no.3
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• pp.108-111
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• 2006

The oxidizer-induced corrosion state and microstructure of surface passive metal-oxide layer greatly influenced on the removal rate of tungsten film according to the slurry chemical composition of different mixed oxidizers. In this paper, the actual polishing mechanism and pH-potential equilibrium diagram obtained from potentiodynamic polarization curve were electrochemically compared. An electrochemical corrosion effect implies that slurries with the highest removal rate (RR) have the high dissolution rate.

• Ceramist
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• v.4 no.1
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• pp.5-13
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• 2001

차세대 ULSI 소자의 다층금속배선을 위한 저유전 물질중에서, 기존의 절연막인 TEOS-$SiO_2$ 증착 장비 및 공정을 최대한 이용할 수 있으며, 물성 또한 TEOS oxide와 유사하다는 점에서 적용 시점을 앞당길 수 있는 SiOF 박막과 SiOC 박막의 특성에 대해 고찰해 보았다. 1세대 저유전 물질이라 할 수 있는 SiOF는 후속공정에도 안정적인 상태의 박막을 얻기 위해서는 3.0이하의 유전상수를 얻는 것이 불가능한 반면, SiOC는 3.0 이하의 유전상수를 가지는 안정적인 박막을 얻을 수 있다. SiOC 물질은 저밀도의 단일물질로서, 물질 내부에 후속공정에 영향을 미칠만한 기공을 포함하지 않기 때문에 후속 CMP 공정에 적합하였으며, $450^{\circ}C$이하의 열 공정에서도 응력변화 및 박막성분 탈착이 거의 일어나지 않는 점 또한 SiOC 박막의 우수한 후속공정 적합성을 보여주는 결과였다. 이러한 결과를 종합하여 볼 때, 현재 사용되고 있는 1세대 저유전 물질인 SiOF 박막을 대체할 차세대 저유전 물질로 SiOC 물질이 유망하며, 이는 3.0 이하의 유전상수를 요구하는 Gb DRAM 소자나 보다 빠른 동작속도가 생명인 논리회로(logic circuit) 소자에 적용될 경우 큰 소자특성 개선이 기대된다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.1
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• pp.11-19
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• 2003

A micro sensor array with 4 discrete sensors integrated on a microhotplate was developed for identifying the kinds and quantities of explosive gases. The sensor array consisited of four tin oxide-based thin films with the high and broad sensitivity to the tested explosive gases and uniform thermal distribution on the plate. The microhotplate, using silicon substrate with N/O/N membrane, dangling in air by Al bonding wires, and controlling the thickness by chemical mechanical process (CMP), has been designed and fabricated. By employing the sensitivity signal of the sensor array at 40$0^{\circ}C$, we could reliably classily the kinds and quantities of the explosive gases like butan, propane, LPG, and carbon monoxide within the range of threshold limit values (TLVs), employing principal component analysis (PCA).

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2004.07b
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• pp.1278-1282
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• 2004

수열처리법으로 nano-sized $CeO_2$ 입자를 $Al_3O_3$ 입자의 표면에 균일하게 코팅하여 $AL_2O_3/O_2$ composite 연마 입자를 제조하었다. 제조된 $Al_2O_3\CeO_2$ composite 입자의 뭍성을 TEM, XRD, zeta potential analyzer 및 particle size analyzer로 측징하였다. $Al_2O_3/CeO_2$ composite 입자와 구성된 슬러리와 비교 시료로서 $Al_2O_3$와 $CeO_2$ 입자를 혼합한 슬러리를 사용하여 thermal oxide film에 대한 연마특성을 평가하였다. 연마슬러리에 포함된 $A1_2O_3/CeO_2$ composite 입자와 $Al_2O_3$와 $CeO_2$ 혼합입자에서 나노 크기의 세리아 입자가 sub-micron 크기의 알루미나 입자의 표면에 균일하게 코팅되므로서 $Al_2O_3$ 단일 성분의 슬러리에 비해 removal rate(RR)는 106 nm/min, WIWNU는 $8\sim9%$, roughness는 $2.6{\AA}$의 향상된 연마 특성을 나타내었다. 알루미나 입자의 불규칙한 형상 때문에 $Al_2O3/CeO_2$ composite 슬러리와 $Al_2O_3$ 와 $CeO_2$ 혼합슬러리의 연마 특성이 비슷한 수준을 나타내었다.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.20 no.3
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• pp.234-239
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• 2007

This paper describes the TiW ohmic contact characteristics under the surface treatment of the polycrystalline 3C-SiC thin film grown on $SiO_2/Si(100)$ wafers by APCVD. The poly 3C-SiC surface was polished by using CMP(chemical mechanical polishing) process and then oxidized by wet-oxidation process, and finally removed SiC oxide layers. A TiW thin film as a metalization process was deposited on the surface treated poly 3C-SiC layer and was annealed through a RTA(rapid thermal annealing) process. TiW/poly 3C-SiC was investigated to get mechanical, physical, and electrical characteristics using SEM, XRD, XPS, AFM, optical microscope, I-V characteristic, and four-point probe, respectively. Contact resistivity of the surface treated 3C-SiC was measured as the lowest $1.2{\times}10^{-5}{\Omega}cm^2$ at $900^{\circ}C$ for 45 sec. Therefore, the surface treatments of poly 3C-SiC are necessary to get better contact resistance for extreme environment MEMS applications.

• Korean Journal of Materials Research
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• v.9 no.2
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• pp.124-131
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• 1999

Copper film, which is expected to be used as interconnection material for 1 giga DRAM integrated circuits was deposited on hole and trench patterns by Metal Organic Chemical Vapor Deposition(MOCVD) method. After a reflow process, contact and L/S patterns were filled by copper and the characteristics of the Cu reflow process were investigated. When deposited Cu films were reflowed, grain growth and agglomeration of Cu have occurred in surfaces and inner parts of patterns as well as complete filling in patterns. Also Cu thin oxide layers were formed on the surface of Cu films reflowed in $O_2$ambient. Agglomeration and oxidation of Cu had bad influence on the electrical properties of Cu films especially, therefore, their removal and prevention were studied simultaneously. As a pattern size is decreased, preferential reflow takes place inside the patterns and this makes advantages in filling patterns of deep submicron size completely. With Cu reflow process, we could fill the patterns with the size of deep sub-micron and it is expected that Cu reflow process could meet the conditions of excellent interconnection for 1 giga DRAM device when it is combined with Cu MOCVD and CMP process.