• Journal of electromagnetic engineering and science
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• v.17 no.2
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• pp.98-104
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• 2017

This work describes the development and comparison of two phase-locked loops (PLLs) based on a 65-nm CMOS technology. The PLLs incorporate two different topologies for the output voltage-controlled oscillator (VCO): LC cross-coupled and differential Colpitts. The measured locking ranges of the LC cross-coupled VCO-based phase-locked loop (PLL1) and the Colpitts VCO-based phase-locked loop (PLL2) are 119.84-122.61 GHz and 126.53-129.29 GHz, respectively. Th e output powers of PLL1 and PLL2 are -8.6 dBm and -10.5 dBm with DC power consumptions of 127.3 mW and 142.8 mW, respectively. Th e measured phase noise of PLL1 is -59.2 at 10 kHz offset and -104.5 at 10 MHz offset, and the phase noise of PLL2 is -60.9 dBc/Hz at 10 kHz offset and -104.4 dBc/Hz at 10 MHz offset. The chip sizes are $1,080{\mu}m{\times}760{\mu}m$ (PLL1) and $1,100{\mu}m{\times}800{\mu}m$ (PLL2), including the probing pads.

• Journal of Advanced Navigation Technology
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• v.15 no.4
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• pp.596-601
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• 2011

This paper has presented research results for the switching mode class E frequency multiplier that has simple circuit structure and high efficiency. Frequency multiplication is coming from the nonlinearity of the active component, and this paper models the FET active component as a simple switch and some parasitics to analyze the characteristics. The matching component parameters for the class E frequency doubler have been derived with modeling the FET as a input controlled switch and some parasitics. A circuit simulator, ADS, is used to simulate the output voltage and current waveform and efficiency with the variation of the parasitic values. With 2.9GHz input and 2V bias, the drain efficiency has been decreased from 98% to 28% with changing the parasitic capacitance from 0pF to 1pF at 5.8GHz output, which shows that the parasitic capacitance CP has the most significant effect on the efficiency among the parasitics of FET.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.22 no.6
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• pp.116-126
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• 2008

This paper describes the Dual-band WLAN transmitter with 2.4[GHz], 5[GHz]. Dual-band WLAN transmitter was designed at 2.4[GHz] and 5[GHz]. The Dual-band WLAN transmitter has a amplifier which operate at 2.4[GHz] and 5[GHz] frequency and two VCO(Voltage Controlled Oscillator) or VCO has a wide scope of frequency. these problem cause a size and a power consumption, The Dual-band WLAN transmitter module was proposed to solve these. the transmitter was designed to get output signals of IEEE 802.11a's 5.8[GHz] band signal using frequency multiplication way or to act a amplifier about the 2.4[GHz] band signal of IEEE 802.11b/g, according to inputed frequency and bias voltage that a eve using single transmission block. The output spectrum get the improved specification of ACPR of 4[dB], 6[dB], 16[dB] at +11[MHz], +20[MHz], +30[MHz] offset of center frequency compared to no linearization, was satisfied to transmit spectrum mask of IEEE 802.11a wireless Lan.

• Journal of the Korean Ceramic Society
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• v.30 no.9
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• pp.761-767
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• 1993

Electrical and mechanical properties of Pb(Mg, Te, Mn, Nb)O3-PZT ceramics are investigated as a function of CeO2 addition (0 to 0.3wt%), and the output characteristics of piezoelectric transformer are also presented. The grain size decreased and the shapes of particles were more uniform with the addition of CeO2. The coercive electric field(9500V/cm), mechanical quality factor (2500) and bend strength (1065kg/$\textrm{cm}^2$) were improved by addition of CeO2 0.2wt%. After repetition of a number of stress cycles, the degradation of k33 was not found in this sample. The voltage step-up ratio (Vdc/Vrms) of piezoelectric ceramic transformer (half wavevoltage doubler, load resistor 100M.ohm) was about 950 in a linear region, its value was relatively higher than other materials.

• Journal of the Korea Institute of Military Science and Technology
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• v.9 no.2 s.25
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• pp.103-110
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• 2006

We present a W-band radiometer to detect the metal targets on the ground environment. The type of the designed radiometer is the total power radiometer(TPR) for the simple configuration. The front end of the TPR consists of only the Mixer and LO for miniaturizing the system. Because the radiometer system does not use the low noise amplifier, we use matching circuits and a diode detector configured as a voltage doubler to compensate the degradation of sensitivity. We solve the temperature variation problems by filtering the reference voltages of the radiometer output signals. Through some experiments, we have verified that the designed radiometer system has good performances in detecting metal targets lying at several hundred meters.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.5C
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• pp.530-534
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• 2002

In the thesis, For improving the Stability of VCHRO(Voltage Controlled Hair-pin Resonator Oscillator) the new structure using the parallel feedback of the second harmonic is proposed for self-phase locking effect. This module is composed of wilkinson divider, frequency doubler, directional coupler, and bandpass filter using a hair-pin resonator, which are integrated into miniaturized hybrid circuit. The module exhibits output power of 2.5 dBm at 19.5 GHz, -29.83 dBc fundamental frequency suppression and -76.52 dBc/Hz phase noise at 10 kHz offset frequency from carrier of center frequency 19.5 GHz.

• Journal of Power Electronics
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• v.16 no.3
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• pp.1209-1217
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• 2016

This paper presents a novel charge pump scheme that combines the advantages of Fibonacci and Dickson charge pumps to obtain 30 V voltage for display driver integrated circuit application. This design only requires four external capacitors, which is suitable for a small-package application, such as smart card displays. High-amplitude (<6.6 V) clocks are produced to enhance the gate drive of a Dickson charge pump and improve the system's current drivability by using a voltage-doubler charge pump with a pulse skip regulator. This regulation engages many middle-voltage devices, and approximately 30% of chip size is saved. Further optimization of flying capacitors tends to decrease the total chip size by 2.1%. A precise and simple model for a one-stage Fibonacci charge pump with current load is also proposed for further efficiency optimization. In a practical design, its voltage error is within 0.12% for 1 mA of current load, and it maintains a 2.83% error even for 10 mA of current load. This charge pump is fabricated through a 0.11 μm 1.5 V/6 V/32 V process, and two regulators, namely, a pulse skip one and a linear one, are operated to maintain the output of the charge pump at 30 V. The performances of the two regulators in terms of ripple, efficiency, line regulation, and load regulation are investigated.

• The Transactions of the Korean Institute of Power Electronics
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• v.15 no.2
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• pp.150-158
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• 2010

The operational characteristics of a resonant DC/DC converter, which can harvest thermoelectric energy, is analyzed, depending on the relative magnitudes of the input voltage and the load voltage. The resonant converter consists of LC resonant circuit connected to DC input source and a resonant pulse converter in which the input energy is transferred to the load as the resonant capacitor voltage is peak. The resonant capacitor doubles the input voltage by the resonance phenomenon. By the relative magnitude between the input voltage and the output voltage, the resonant DC/DC converter operates in three different modes. For boost mode, the peak voltage of the resonant capacitor is smaller than the load voltage. For hybrid mode, the peak voltage of the resonant capacitor is bigger than the load voltage and every switching period has both the boost mode and the direct mode. For the direct mode, the input voltage is bigger than the load voltage and the converter transfers directly the input energy to the load without the switching operation. Operation principles and the feasibility of the converter for the thermoelectric energy harvesting are verified with PSPICE simulation and experiment.

• Proceedings of the KIEE Conference
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• 2008.10b
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• pp.524-525
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• 2008

본 논문에서는 각각의 스위치 시비율(Duty ratio)의 변화를 이용한 기존의 풀-브릿지 방식과 두 쌍의 스위치 신호 위상 변화를 이용한 위상천이 풀-브리지(Phase-shift Full-bridge) 방식의 차이점을 서술하였다. 위상천이 컨버터의 안정성을 연구하기 위하여, 출력 전류의 맥동(ripple)을 작게 하는 배전류(Current Doubler) 정류회로와 효율을 높이기 위한 동기 정류기(Synchronous Rectifier)를 포함한 평균화 된 스위치 모델을 제안한다. 이 모델을 이용하여 PSPICE 시뮬레이션을 통해 안정성을 고찰하였으며 1.2kW급 170-14V DC-DC 컨버터의 시작품을 제작 후 시뮬레이션 결과와 시작품 결과를 비교하였다. 시뮬레이션의 경우 위상여유는 $58^{\circ}$ 시작품의 위상여유는 $68^{\circ}$로 나타났으며 교차주파수는 12kHz로 동일하게 나오는 것을 확인하였다. 따라서 제안한 시뮬레이션 모델을 이용하여 실제 회로의 안정성을 예측할 수 있으며 이를 실제 회로 제작에 활용 할 수 있다.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.22 no.2
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• pp.148-153
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• 2011

In this paper, an inverse class E frequency multiplier has been designed to generate 5.8 GHz wireless LAN signal by multiplying 2.9 GHz input. The inverse class E frequency multiplier is operating with low inductance value and low peak drain voltage than the class E frequency multiplier. Measurement shows the output power of 21 dBm, the mutiplier gain of 6 dB, and the PAE(Power Added Efficiency) of 35 % with 15 dBm input power.