• ETRI Journal
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• v.34 no.5
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• pp.727-733
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• 2012

This paper demonstrates a new driving scheme that allows reducing the supply voltage of data drivers for low-power active matrix organic light-emitting diode (AMOLED) displays. The proposed technique drives down the data voltage range by 50%, which subsequently diminishes in the peak power consumption of data drivers at the full white pattern by 75%. Because the gate voltage of a driving thin film transistor covers the same range as a conventional driving scheme by means of a level-shifting scheme, the low-data supply scheme achieves the equivalent dynamic range of OLED currents. The average power consumption of data drivers is reduced by 60% over 24 test images, and power consumption is kept below 25%.

• 한국정보디스플레이학회:학술대회논문집
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• 2007.08a
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• pp.871-874
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• 2007

We have synthesized a novel fully soluble and low-temperature processable polyimide gate insulator (KSPI) through one-step condensation polymerization. For the preparation of KSPI, 5- (2,5-dioxytetrahydrofuryl)-3-methly-3-cyclohexene- 1,2-dicarboxylic anhydride (DOCDA) and 4,4- diaminodiphenylmethane (MDA) were used as monomers and fully imidized KSPI was completely soluble in organic solvents like ${\gamma}-butyrolactone$ and 2-butoxyethanol, etc.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2007.11a
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• pp.492-493
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• 2007

Organic field-effect transistors (OFETs) are of interest for use in widely area electronic applications. We fabricated a copper phthalocyanine(CuPc) based field-effect transistor with different metal electrode. So we need the effect of the substituent group attached to the phthalocyanine on the surface potential was investigated by Kelvin probe method with varying temperature of the substrate. We were obtained the positive shift of the surface potential for CuPc thin film. We observed the electron displacement at the interface between Au electrode and CuPc layer and we were confirmed by the surface potential measurement.

• Journal of the Korean Applied Science and Technology
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• v.25 no.3
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• pp.388-394
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• 2008

본 논문에서는 용액 공정을 이용한 고분자 절연층을 갖는 top-gate 구조의 펜타센 박막 트랜지스터(Thin Film Transistor, TFT)의 특성을 연구하였다. Top-gate 구조의 펜타센 TFT 제작에 앞서 유기 반도체인 펜타센의 결정성 성장을 돕기 위해서 가교된 PVP (cross-linked poly(4-vinylphenol))를 유리 기판 상에 스핀 코팅을 이용하여 형성한 후, 노광 공정을 통해 니켈/은 구조를 갖는 채널 길이 $10{\mu}m$의 소오스, 드레인 전극을 형성하였다. 그리고 열 증착을 이용하여 60 nm 두께의 펜타센 층을 성막하였고, 고분자 절연체로서 PVA(polyvinyl alchol) 또는 가교된 PVA를 용액공정인 스핀 코팅을 이용하여 형성한 후 열 증착으로 알루미늄 게이트 전극을 성막하였다. 이로써 제작된 소자들의 전기적 특성을 확인한 결과 가교된 PVA를 사용한 펜타센 TFT 보다 PVA를 게이트 절연체로 사용한 소자가 전기적 특성이 우수한 것으로 관찰되었다. 이는 PVA의 가교 공정에 의한 펜타센 박막의 성능 퇴화에 기인한 것으로 사료된다. 실험 결과 $0.9{\mu}m$ 두께의 PVA 게이트 절연막을 사용한 top-gate 구조의 펜타센 TFT의 전계 효과 이동도와 문턱전압, 그리고 전류 점멸비는 각각, 약 $3.9{\times}10^{-3}\;cm^2/Vs$, -11.5 V, $3{\times}10^5$으로써 본 연구에서 제안된 소자가 용액 공정형 top-gate 유기 TFT 소자로서 우수한 성능을 나타냄을 알 수 있었다.

• Journal of Integrative Natural Science
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• v.4 no.4
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• pp.311-314
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• 2011

Application of self-assembled monolayers (SAMs) to the fabrication of organic thin film transistor has been recently reported very often since it can help to provide ohmic contact between films as well as to form simple and effective electrode pattern. Accordingly, quality of these ultra-thin films is becoming more imperative. In this study, in order to manufacture a high quality SAM pattern, a hydrophobic alkylsilane monolayer and a hydrophilic aminosilane monolayer were selectively coated on $SiO_2$ surface through the consecutive procedures of a micro-contact printing (${\mu}CP$) and dip-coating methods under extremely dry condition. On a SAM pattern cleaned with SC1 solution immediately after ${\mu}CP$, poly(3,4-ethylenedioxythiophene) (PEDOT) source and drain electrode array were very selectively and nicely vapour phase polymerized. On the other side, on a SC1-untreated SAM pattern, PEDOT array was very poorly polymerized. It strongly suggests that the SC1 cleaning process effectively removes unwanted contaminants on SAM pattern, thereby resulting in very selective growth of PEDOT electrode pattern.

• ETRI Journal
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• v.31 no.6
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• pp.653-659
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• 2009

We have investigated the channel protection layer (PL) effect on the performance of an oxide thin film transistor (TFT) with a staggered top gate ZnO TFT and Al-doped zinc tin oxide (AZTO) TFT. Deposition of an ultra-thin PL on oxide semiconductor films enables TFTs to behave well by protecting the channel from a photo-resist (PR) stripper which removes the depleted surface of the active layer and increases the carrier amount in the channel. In addition, adopting a PL prevents channel contamination from the organic PR and results in high mobility and small subthreshold swings. The PL process plays a critical role in the performance of oxide TFTs. When a plasma process is introduced on the surface of an active layer during the PL process, and as the plasma power is increased, the TFT characteristics degrade, resulting in lower mobility and higher threshold voltage. Therefore, it is very important to form an interface using a minimized plasma process.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.02a
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• pp.277-277
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• 2012

PCDTBT (Poly[N-9''-hepta-decanyl-2,7-carbazole-alt-5,5-(4',7'-di-2-thienyl-2',1',3'-benzothiadiazole)]) is an attractive material as a semiconducting polymer for organic thin film transistor (OTFT) and organic solar cell (OSC). High power conversion efficiency (~6%) under simulated AM 1.5G solar illumination of bulk-heterojunction solar cell with PCDTBT and [6,6]-phenyl C60 butyric acid methyl ester (PC61BM) blend was reported. In OSC, it is known that the band alignment at the interface between donor and acceptor is critical. Therefore, we studied the interfacial electronic structures of PCDTBT and PC61BM. The polymers are deposited by electro-spray on gold and In-situ x-ray and ultraviolet photoelectron spectroscopy measurements revealed the interfacial electronic structures. We obtained the energy level alignment between two materials and the different interface formation was observed with different deposition order.

• ETRI Journal
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• v.35 no.4
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• pp.734-737
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• 2013

Nonvolatile ferroelectric poly(vinylidene fluoride-co-trifluoroethylene) memory based on an organic thin-film transistor with inkjet-printed dodecyl-substituted thienylenevinylene-thiophene copolymer (PC12TV12T) as the active layer is developed. The memory window is 4.5 V with a gate voltage sweep of -12.5 V to 12.5 V. The field effect mobility, on/off ratio, and gate leakage current are 0.1 $cm^2/Vs$, $10^5$, and $10^{-10}$ A, respectively. Although the retention behaviors should be improved and optimized, the obtained characteristics are very promising for future flexible electronics.

• Journal of the Korean Applied Science and Technology
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• v.24 no.1
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• pp.54-60
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• 2007

이 논문에서는 게이트 절연막 위에 vapor deposition polymerization(VDP)방법을 사용하여 성막한 유기 점착층을 진공 열증착하여 유기 박막 트랜지스터(OTFTs)소자를 제작할 수 있음을 증명하였다. 우리가 제작한 Staggered-inverted top-contact 구조를 사용한 유기 박막 트랜지스터는 전기적 output 특성이 포화 영역안에서는 포화곡선을, triode 영역에서는 비선형적인 subthreshold를 확실히 볼 수 있음을 발견했다. $0.2{\mu}m$ 두께를 가진 게이트 절연막위에 유기 점착층을 사용한 OTFTs의 장 효과 정공의 이동도와 문턱전압, 그리고 절멸비는 각각, 약 0.4cm2/Vs, -0.8V, 106 이 측정되었다. 게이트 절연막의 점착층으로써 폴리이미드의 성막을 위해, 스핀코팅 방법 대신 VDP 방법을 도입하였다. 폴리이미드 고분자막은 2,2bis(3,4-dicarboxyphenyl)hexafluoropropane dianhydride(6FDA)와 4,4'-oxydianiline(ODA)을 고진공에서 동시에 열 증착 시킨 후, 그리고 $150^{\circ}C$에서 1시간, 다시 $200^{\circ}C$에서 1시간 열처리하여 고분자화된 막을 형성하였다. 그리고 점착층이 OTFTs의 전기적 특성에 주는 영향을 설명하기 위해 비교 연구하였다.

• Journal of the Semiconductor & Display Technology
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• v.5 no.1 s.14
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• pp.39-43
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• 2006

The polyvinyl series organic films as gate insulators of thin film transistor(TFT) have been processed and characterized on the polyether sulphone (PES) substrates . The poly-4-vinyl phenol(PVP) and polyvinyl toluene (PVT) were used as solutes and propylene glycol monomethyl ether acetate(PGMEA) as a solvent in the formation of organic insulators. The cross-linking of organic insulators was also attempted by adding the thermosetting material, poly (melamine-co-formaldehyde) as a hardener in the compound. The electrical characteristics measured in the metal-insulator-metal (MIM) structures showed that insulating properties of PVP layers were generally superior to those of PVT layers. Among the layers of PVP series; copolymer PVP(10 wt%), 5wt% cross-linked PVP(10 wt%), copolymer PVP(20 wt%), 5 wt% cross-linked PVP(20 wt%) and 10 wt% cross-linked PVP(20 wt%), the 10 wt% cross-linked PVP(20 wt%) layer showed the lowest leakage current of 1.2 pA at ${\pm}10V$. The ms value of surface roughness and the capcitance per unit area are 2.41 and $1.76nF/cm^2$ in the case of 10 wt% cross-linked PVP(20 wt%) layer, respectively.