• Journal of the Korean Institute of Telematics and Electronics B
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• v.33B no.4
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• pp.148-155
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• 1996

A loop structure optimization algorithm is proposed for generting a set of efficient codes for loop structure in order to optimize RISC compiler codes. Since there are so many loop structure in the program, most of the execution time is used to process looping codes. Thus, reduction of loop instructions is more effective than optimizing codes outside the loop. The proposed algorithm presents a method to combine several different loops into a simple loop. Therefore, rather than executing each loop independently, loops in the program are serached, analyzed, and finally created some relative informtion such as dependency and range. In doing so, the loops in the program can efficiently be recombined and restructured. As a result, the overall execution time for the program of the sequential programming language is reduced.

• International Journal of Internet, Broadcasting and Communication
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• v.9 no.1
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• pp.29-34
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• 2017

Over the past several decades, embedded system and flight control computer technologies have been evolved to meet the diverse needs of the mobile device market. Current embedded systems are at the heart of technologies that can take advantage of small-sized specialized hardware while still providing high-efficiency performance at low cost. One of these key technologies is multiple memory banks. For example, a dual memory bank can provide two times more memory bandwidth in the same memory space. This benefit take lower cost to provide the same bandwidth. However, there is still few software technologies to support the efficient use of multiple memory banks. In this study, we present a technique to efficiently exploit multiple memory banks by software support. Specifically, our technique use an interference graph to optimally allocate data to different memory banks by an optimizing compiler. As a result, the execution time can be improved upto 7% with the proposed technique.

• IEMEK Journal of Embedded Systems and Applications
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• v.8 no.5
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• pp.255-264
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• 2013

Resolving of memory access latency is one of the most important problems in modern embedded system design. Recently, tons of studies are presented to reduce and hide the access latency. Burst/page data transfer modes are representative hardware techniques for achieving such purpose. The burst data transfer capability offers an average access time reduction of more than 65 percent for an eight-word sequential transfer. However, solution of utilizing such burst data transfer to improve memory performance has not been accomplished at commercial level. Therefore, this paper presents a new technique that provides the maximum utilization of burst transfer for memory accesses with local variables in code by reorganizing variables placement.

• IEMEK Journal of Embedded Systems and Applications
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• v.12 no.3
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• pp.159-167
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• 2017

Software safety is a key issue in embedded system of automotive and aviation industries. Various software testing approaches have been proposed to achieve software safety like ISO26262 Part 6 in automotive environment. In spite of one of the classic and basic approaches, stack memory is hard to estimating exactly because of uncertainty of target code generated by compiler and complex nested interrupt. In this paper, we propose an approach of analyzing the maximum stack usage statically from target binary code rather than the source code that also allows nested interrupts for determining the exact stack memory size. In our approach, determining maximum stack usage is divided into three steps: data extraction from ELF file, construction of call graph, and consideration of nested interrupt configurations for determining required stack size from the ISR (Interrupt Service Routine). Experimental results of the estimation of the maximum stack usage shows proposed approach is helpful for optimizing stack memory size and checking the stability of the program in the embedded system that especially supports nested interrupts.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 1999.05a
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• pp.192-197
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• 1999

Programmers who write distributed programs are faced with a dilemma when writing the systems communication code. If the code is written by hand or partly by hand, then the speed of the application may be maximized, but the human effort required to implement and maintain the system is greatly increased. On the other hand, if the code is generated using a CORBA IDL compiler then the programmer effort will be reduced, but the performance of the application may be poor. So we need the optimizing the code generated by CORBA IDL compiler. We introduce the techniques which have been used by typical programming languages into compilation of IDL. We separate the phase of compilation into three phase. The first phase parses interface definition in IDL, manages nested scope and generates AST(Abstract Syntax Tree). The second phase implements the optimization. The third phase generates the code in target language. In this paper, we focus on the first phase. We separate interface definition into interface and message representation from AST. This supports the separate optimization of code in second phase.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.34 no.12B
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• pp.1380-1386
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• 2009

In this paper, we propose a CQS(Calendar Queue Scheduler) architecture which was designed for processing multimedia and timing traffic in home network. With various characteristics of the increased traffic flowed in home such as VoIP, VOD, IPTV, and Best-efforts traffic, the needs of managing QoS(Quality of Service) are being discussed. Making a group regarding application or service is effective to guarantee successful QoS under the restricted circumstances. The proposed design is aimed for home gateway corresponding to the end points of receiver on end-to-end QoS and eligible for supporting multimedia traffic within restricted network sources and optimizing queue sizes. Then, we simulated the area for each module and each memory. The area for each module is referenced by NAND($2{\times}1$) Gate(11.09) when synthesizing with Magnachip 0.18 CMOS libraries through the Synopsys Design Compiler. We verified the portion of memory is 85.38% of the entire CQS. And each memory size is extracted through CACTI 5.3(a unit in mm2). According to the increase of the memory’sentry, the increment of memory area gradually increases, and defining the day size for 1 year definitely affects the total CQS area. In this paper, we discussed design methodology and operation for each module when designing CQS by hardware.

• Journal of KIISE:Software and Applications
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• v.32 no.8
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• pp.819-833
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• 2005

Code size reduction is ever becoming more important for compilers targeting embedded processors because these processors are often severely limited by storage constraints and thus the reduced code size can have a positively significant Impact on their performance. Various code size reduction techniques have different motivations and a variety of application contexts utilizing special hardware features of their target processors. In this work, we propose a novel technique that fully utilizes a set of hardware instructions, called the multiple load/store (MLS), that are specially featured for reducing code size by minimizing the number of memory operations in the code. To take advantage of this feature, many microprocessors support the MLS instructions, whereas no existing compilers fully exploit the potential benefit of these instructions but only use them for some limited cases. This is mainly because optimizing memory accesses with MLS instructions for general cases is an NP-hard problem that necessitates complex assignments of registers and memory off-sets for variables in a stack frame. Our technique uses a couple of heuristics to efficiently handle this problem in a polynomial time bound.

• The Transactions of the Korea Information Processing Society
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• v.5 no.5
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• pp.1345-1356
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• 1998

Prolog tailoring technique, an optimization method to improve the execution speed of a procedure, is proposed in this paper. When a procedure is frequently and repeatedly called and the machine has a lot of callee-saved registers, optimizing prolog and epilog can become an important step of optimization. Epilg tailoring supported by IBM XL C Compiler has been known to improve procedure's execution speed by reducing register restore instructions on execution paths, but no algorithms for prolog tailoring has been proposed yet. The prolog generated by the prolog tailoring algorithm proposed in this paper executes considerably smaller number of register save instructions at run-time. This means the total number of instructions to be executed is decreased resulting in an improvement on the procedure's execution speed. To maintain the correctness of code, prolog code should not be inserted inside diamond structures of loop structures. This paper proposes a prolog tailoring technique which generates register save instructions at the best position in a control flow graph while not allowing the insertion of any prolog code inside diamond structures of loop structures.