• Journal of Electrical Engineering and information Science
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• v.2 no.3
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• pp.41-50
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• 1997

In this paper, we describe the design, implementation and evaluation for a multimedia conferencing system with intramedia and intermedia synchronization support between audio and video. The synchronization mechanism proposed here is capable of dynamically adapting to various network conditions thus providing an optimized QoS. In realizing the system based on this mechanism, NeVoT on Mbone is used for audio and VIC for video. Furthermore a synchromization controller is designed and realized with a unique process in supporting intermedia synchronization. Each media agents handling its media stream are modified with intramedia synchronization function. And a communicative function between media agents and synchronization controller is added as well for intermedia synchronization function. Each media agents function reports its buffering status to the synchronization control process which in turn send out optimized buffering delay value thus supporting intermedia synchronization. The realized system is configured and tested on Ethernet and ATM network where performance measurements were performed and its effective synchronization support has been assured.

• Korean Journal of Computational Design and Engineering
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• v.12 no.6
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• pp.405-412
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• 2007

It's difficult for manufacturers to derive a new design from the demands of consumers as quickly as possible and a designer carries out design operation using insufficient resources in initial design. To carry out initial design process efficiently for an excavator front group, it is necessary for a designer to manage lots of parameter with an existing knowledge or with in-house know-how and develop function module that calculates working range and excavator force. By doing so, it will bring up the optimized values of parameters based on the DOE in the early design stage. In this paper, a new approach to improve the process with optimized parameters is proposed to reduce a product development time of the excavator front design.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1998.06a
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• pp.527-533
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• 1998

An optimized PWM switching strategy for an induction motor voltage control is developed and demonstrated. Space vector modulation in voltage source inverter offers improved DC-bus utilization and reduced commutation losses, and has been therefor recognizedas the perfered PWM method, especially in the case of digital implementation. Three-phase invertor voltage control by space vector modulation consists of switching between the two active and one zero voltage vector by using the proposed optimal PWM algorithm. The prefered switching sequence is defined as a function of the modulation index and period of a carrier wave. The sequence is selected by suing the inverter switching losses and the current ripple as the criteria. For low and medium power application, the experimental results indicate that good dynamic response and reduced harmonic distortion can be achieved by increasing switching frequency.

• Journal of information and communication convergence engineering
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• v.13 no.3
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• pp.145-151
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• 2015

We describe in this paper a hardware-based improvement scheme of a real-time automatic speech recognition (ASR) system with respect to speed by designing a parallel feature extraction algorithm on a Field-Programmable Gate Array (FPGA). A computationally intensive block in the algorithm is identified implemented in hardware logic on the FPGA. One such block is mel-frequency cepstrum coefficient (MFCC) algorithm used for feature extraction process. We demonstrate that the FPGA platform may perform efficient feature extraction computation in the speech recognition system as compared to the generalpurpose CPU including the ARM processor. The Xilinx Zynq-7000 System on Chip (SoC) platform is used for the MFCC implementation. From this implementation described in this paper, we confirmed that the FPGA platform is approximately 500× faster than a sequential CPU implementation and 60× faster than a sequential ARM implementation. We thus verified that a parallelized and optimized MFCC architecture on the FPGA platform may significantly improve the execution time of an ASR system, compared to the CPU and ARM platforms.

• Journal of Korea Society of Digital Industry and Information Management
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• v.15 no.4
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• pp.85-92
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• 2019

This paper presents a SDR-based Long Term Evolution Advanced (LTE-A) Physical Downlink Shared Channel (PDSCH) decoder using a multicore Digital Signal Processor (DSP). For decoder implementation, multicore DSP TMS320C6670 is used, which provides various hardware accelerators such as turbo decoder, fast Fourier transformer and Bit Rate Coprocessors. The TMS320C6670 is a DSP specialized in implementing base station platforms and is not an optimized platform for implementing mobile terminal platform. Accordingly, in this paper, the hardware accelerator was changed to the terminal implementation to implement the LTE-A PDSCH decoder supporting the multi-antenna and the functions not provided by the hardware accelerator were implemented through core programming. Also pipeline using multicore was implemented to meet the transmission time interval. To confirm the feasibility of the proposed implementation, we verified the real-time decoding capability of the PDSCH decoder implemented using the LTE-A Reference Measurement Channel (RMC) waveform about transmission mode 2 and 3.

• KIPS Transactions on Computer and Communication Systems
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• v.11 no.6
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• pp.167-174
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• 2022

PIPO lightweight block ciphers were announced in ICISC'20. In this paper, a single-block optimization implementation and parallel optimization implementation of PIPO lightweight block cipher ECB, CBC, and CTR operation modes are performed on a 32-bit RISC-V processor. A single block implementation proposes an efficient 8-bit unit of Rlayer function implementation on a 32-bit register. In a parallel implementation, internal alignment of registers for parallel implementation is performed, and a method for four different blocks to perform Rlayer function operations on one register is described. In addition, since it is difficult to apply the parallel implementation technique to the encryption process in the parallel implementation of the CBC operation mode, it is proposed to apply the parallel implementation technique in the decryption process. In parallel implementation of the CTR operation mode, an extended initialization vector is used to propose a register internal alignment omission technique. This paper shows that the parallel implementation technique is applicable to several block cipher operation modes. As a result, it is confirmed that the performance improvement is 1.7 times in a single-block implementation and 1.89 times in a parallel implementation compared to the performance of the existing research implementation that includes the key schedule process in the ECB operation mode.

• Proceedings of the IEEK Conference
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• 2000.06a
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• pp.65-68
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• 2000

In this paper, design parameters are investigated and design procedure is established for PCS mobile station, especially for receiver RF block. And simulation environment to analyze parameters of the receiver RF block to determine whether it satisfies the receiver standard, IS-98C, is calculated. Design parameters are simulated and optimized. With simulated results, PCS mobile station is implemented and tested. Measured results show good agreement with simulation Design procedure can be used to get optimum characteristics for each of receiver block. By using optimum characteristics, mobile station can be designed more efficiently.

• Journal of Biomedical Engineering Research
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• v.9 no.2
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• pp.239-246
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• 1988

This paper describes the design and implementation of personal computer assisted karyotyping system of Giemsa stained chromosomes. The system consists of an Image Acquisition Module being capable of $256 {\times} 256$ pixels and its relevent software modules optimized for karyotyping. The results of karyotyping using this system with an image of chromosomes taken from the Rana Amurensis are acceptable. As a result of this study we can save our load oweing to the conventional hand- karyotyping and the high-cost computer.

• Proceedings of the IEEK Conference
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• 2000.11b
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• pp.341-344
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• 2000

Several new via structures in printed circuit boards are proposed, fabricated and characterized in RF regime. The new structure with a larger inductance component in the bottom layer shows 3㏈ improvement over the conventional structure. The ADS simulation with model parameters extracted from 3D fie]d solver matches with the characterization of these vias

• Proceedings of the IEEK Conference
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• 2003.07a
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• pp.517-520
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• 2003

Orthogonal Frequency Division Multiplexing (OFDM) is a promising technology for high speed multimedia communication in a frequency selective multipath channel. In this paper, Software IPs for the synchronizer of IEEE 802.11a Wireless LAN system are designed and optimized for TI's TMS320C6201 fixed point DSP. As a result of the execution cycles of the target DSP for each functions of the system, an efficient HW/SW partitioning method can be considered.