• Proceedings of the KIEE Conference
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• 1987.07a
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• pp.403-406
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• 1987

CMOS operational amplifier is most useful building bloch in analog circuit. This paper represents the analysis and design method of CMOS OP AMP to use general purpose such as the A/D and D/A converter, PCM encoder and decoder etc. The required specifications is obtained by changing W/L ration of CMOS devices. The design procedure must be iterative in as much as it is almost impossible to relate all specifications simultaneously. This is performanced with IBM-PC XT by using SPICE(SIMULATION PROGRAM WITH INTEGRATED CIRCUIT EMPHASIS)program.

• Proceedings of the Optical Society of Korea Conference
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• 1989.02a
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• pp.20-25
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• 1989

The nonlinear, time dependent photon transport equations of Frantz and Nodvik, which describe the amplification of an optical pulse in an active medium, are modified to a simpler equation which describes only the amplification of energy. with this equation, the output energy of the high power YLF(Nd3+)-Phosphate Glass(Nd3+) Laser System is calculated. When the stored energy density Est is 0.10J/㎤, 0.16J/㎤, 0.228J/㎤, and 0.50J/㎤, and with the assumption of uniform population inversion density, the final output energy of this laser system is 5.38J, 176J, 317J, and 283J, respectively. The gain saturation causes distortion of the output beam. This phenomenon is described in detail at the first three rod amplifier systems in the case of E=0.228J/㎤. The peak current and decay time constant of the flashlamps, which are used to obtain population inversion in the active medium, are investigated. The flashlamp driving circuit which has optimum operational performance should have {{{{ SQRT { LC} }} time about 100$\mu$sec.

• Journal of IKEEE
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• v.22 no.4
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• pp.1025-1030
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• 2018

The proposed modulator is designed by utilizing a conventional structure employing time division technique to realize the 4th order delta-sigma modulator using one op-amp. In order to reduce the influence of KT/C noise, the capacitance in the first and second integrators reused was chosen to be 20pF and capacitance of third and fourth integrators was designed to be 1pF. The stage variable technique in the low power reconfigurable op-amp was used to solve the stability issue due to different capacitance loads for the reduction of KT/C noise. This technique enabled the proposed modulator to reduce the power consumption of 15% with respect to the conventional one. The proposed modulator was fabricated with 0.18um CMOS N-well 1 poly 6 metal process and consumes 305uW at supply voltage of 1.8V. The measurement results demonstrated that SNDR, ENOB, DR, FoM(Walden), and FoM(Schreier) were 66.3 dB, 10.6 bits, 83 dB, 98 pJ/step, and 142.8 dB at the sampling frequency of 256kHz, oversampling ratio of 128, clock frequency of 1.024 MHz, and input frequency of 250 Hz, respectively.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.15 no.2
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• pp.109-116
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• 2022

In this paper, we propose a band rejection filter (BRF) with a state variable filter (SVF) structure to effectively remove the influence of 60 Hz line frequency noise introduced into the sensor system. The conventional BRF of the SVF structure uses an additional operational amplifier (OPAMP) to add a low pass filter (LPF) output and a high pass filter (HPF) output or an input signal and a band pass filter. Therefore, the notch frequency and the notch depth that determine the signal attenuation of the BRF greatly depend on the tolerance of the resistors used to obtain the sum or difference of the signals. On the other hand, in the proposed BRF, since the BRF output is formed naturally within the SVF structure, there is no need for a combination between each port. The notch frequency of the proposed BRF is 59.99 Hz, and it can be confirmed that it is not affected at all by the tolerance of the resistor through the Monte Carlo simulation results. The notch depth also has an average of -42.54dB and a standard deviation of 0.63dB, confirming that normal operation as a BRF is possible. Also, with the proposed BRF, noise filtering was applied to the electrocardiogram (ECG) signal that interfered with 60 Hz noise, and it was confirmed that the 60 Hz noise was appropriately suppressed.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.6
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• pp.91-98
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• 2013

Magnetic sensor chip for measuring bio-magnetism is implemented in $0.18{\mu}m$ CMOS technology. The magnetic sensor chip consists of a small-sized high inductance coil sensor and an instrumentation amplifier (IA). High inductance coil sensor with suitable sensitivity and bandwidth for measurement of bio-magnetic signal is designed using electromagnetic field simulation. Low gm operational transconductance amplifier (OTA) using transconductance reduction techniques is designed for on-chip solution. Output signal sensitivity of magnetic sensor chip is $3.25fT/{\mu}V$ and reference noise of 21.1fT/${\surd}$Hz. Proposed IA is designed along with band pass filters(BPF) to reduce magnetic signal noise by using current feedback techniques. Proposed IA achieves a common mode rejection ratio of 117.5dB while the input noise referred is kept below $0.87{\mu}V$.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.43 no.5 s.311
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• pp.28-35
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• 2006

This paper presents a new 3.3-1 V synchronous buck DC/DC converter that employs CMOS operational transconductance amplifiers (OTAs) as circuit-building blocks. An error amplifier OTA in a PWM circuit is compensated for to improve temperature stability. The temperature coefficient of the transconductance gain of the compensated OTA is less than $150\;ppm/^{\circ}C\;over\;0-100^{\circ}C$. The HSPICE simulation results of the $0.3{\mu}m$ standard CMOS technology show that the efficiency of the proposed converter is as high as 80% in the load current range of 40-125 mA. These results show that the proposed converter is adequate for use in battery-operated systems.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.19 no.1
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• pp.149-155
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• 2015

This paper proposes 5-MS/s 10-bit digital-to-analog converter(DAC) with the improved linearity. The proposed DAC consists of a 10-bit R-2R-based DAC, an output buffer using a differential voltage amplifier with rail-to-rail input range, and a band-gap reference circuit for the bias voltage. The linearity of the 10-bit R-2R DAC is improved as the resistor of 2R is implemented by including the turn-on resistance of an inverter for a switch. The output voltage range of the DAC is determined to be $2/3{\times}VDD$ from an rail-to-rail output voltage range of the R-2R DAC using a differential voltage amplifier in the output buffer. The proposed DAC is implemented using a 1-poly 8-metal 130nm CMOS process with 1.2-V supply. The measured dynamic performance of the implemented DAC are the ENOB of 9.4 bit, SNDR of 58 dB, and SFDR of 63 dBc. The measured DNL and INL are less than +/-0.35 LSB. The area and power consumption of DAC are $642.9{\times}366.6{\mu}m^2$ and 2.95 mW, respectively.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.7 no.1
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• pp.100-105
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• 2003

In this paper, we propose the novel test method effectively to detect short and open faults in CMOS op-amp. The proposed method uses a sinusoidal signal with higher frequency than unit gain bandwidth. Since the proposed test method doesn't need complex algorithm to generate test pattern, the time of test pattern generation is short, and test cost is reduced because a single test pattern is able to detect all target faults. To verify the proposed method, CMOS two-stage operational amplifier with short and open faults is designed and the simulation results of HSPICE for the circuit have shown that the proposed test method can detect short and open faults in CMOS op-amp.

• ETRI Journal
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• v.31 no.5
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• pp.576-584
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• 2009

A novel tunable transconductor is presented. Input transistors operate in the triode region to achieve programmable voltage-to-current conversion. These transistors are kept in the triode region by a novel negative feedback loop which features simplicity, low voltage requirements, and high output resistance. A linearity analysis is carried out which demonstrates how the proposed transconductance tuning scheme leads to high linearity in a wide transconductance range. Measurement results for a 0.5 ${\mu}m$ CMOS implementation of the transconductor show a transconductance tuning range of more than a decade (15 ${\mu}A/V$ to 165 ${\mu}A/V$) and a total harmonic distortion of -67 dB at 1 MHz for an input of 1 Vpp and a supply voltage of 1.8 V.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.12
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• pp.75-84
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• 2001

Due to the high density of integration in current integrated circuit layouts, circuit elements must be designed to minimize the effect of parasitic elements and thereby minimize the factors which can degrade circuit performance. Thus, before making a chip, circuit designers should check whether the extracted netlist is correct, and verify from a simulation whether the circuit performance satisfies the design specifications. In this paper, we propose a new block disassembly technique which can extract the geometric parameters of stacked MOSFETs and the distributed RCs of layout blocks. After applying this to the layout of a folded-cascode CMOS operational amplifier, we verified the connectivity and the effect of the components by simulating the extracted netlist with HSPICE.