• The Transactions of The Korean Institute of Electrical Engineers
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• v.56 no.11
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• pp.1873-1878
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• 2007

Current differential relays may maloperate during magnetic inrush and over-excitation because a significant differential current is produced. To prevent maloperation, the relays adopt some harmonic components included in the differential current. The harmonic restraints may increase the security of a relay but cause the operating time delay of a relay when an internal fault occurs. Moreover, the operating time delay is more increased if a current transformer (CT) is saturated. This paper describes a current differential relaying algorithm for power transformer protection with a compensating algorithm for the secondary current of a CT. The comparative study was conducted with and without the compensating algorithm. The performance of the proposed algorithm was investigated when the measurement CT (C400) and the protection CT (C400) are used. The proposed algorithm can compensate the distorted current of a CT and thus reduce the operating time delay of the relay significantly for an internal fault with CT saturation.

• The Transactions of the Korean Institute of Electrical Engineers D
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• v.53 no.7
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• pp.501-508
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• 2004

In this paper, a coordinated scheduling algorithm is proposed to reduce end-to-end delay in distributed control of systems. For the algorithm, the analysis of practical end-to-end delay in the worst case is performed priory with considering implementation of the systems. The end-to-end delay is composed of the delay caused by multi-task scheduling of operating systems, the delay caused by network communications, and the delay caused by asynchronous timing between operating systems and network communications. Through some simulation tests based on CAN(Controller Area Network), the proposed worst case end-to-end delay analysis is validated. Through the simulation tests, it is also shown that a real-time distributed control system designed to existing worst case delay cannot guarantee end-to-end time constraints. With the analysis, a coordinated scheduling algorithm is proposed here. The coordinated scheduling algorithm is focused on the reduction of the delay caused by asynchronous timing between operating systems and network communications. Online deadline assignment strategy is proposed for the scheduling. The performance enhancement of the distributed control systems by the scheduling algorithm is shown through simulation tests.

• ETRI Journal
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• v.34 no.2
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• pp.210-215
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• 2012

In this paper, a group delay time controller (GDTC) is proposed based on a reflection topology employing a parallel resonator as the reflection termination. The design equations of the proposed GDTC have been derived and validated by simulation and experimental results. The group delay time can be varied by varying the capacitance and inductance at an operating frequency. To show the validity of the proposed circuit, an experiment was performed for a wideband code division multiple access downlink band operating at 2.11 GHz to 2.17 GHz. According to the experiment, a group delay time variation of $3{\pm}0.17$ ns over bandwidth of 60 MHz with excellent flatness is obtained.

• Korea Journal of Hospital Management
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• v.7 no.3
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• pp.44-62
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• 2002

Advanced surgical technology demands more precise, meticulous, and time-consuming procedures. In addition, the patient's preference of tertiary health providers makes over crowding of the University Hospitals. Therefore, it has been necessary to maximize utilization of the operating room of such hospitals to accommodate these requirements. This study, targeting 1,302 surgical cases performed in 22 operating rooms at a university hospital in Seoul from October 8 to November 1, 2001, analyzed reasons for delay, and factors that caused delayed use of operating rooms. This study also assessed that the rate of operating room use would increase if the sources for possible reform were improved. 1. Among total of 1,302 cases of surgery, the incidence of surgeries in which there were no time delays and no factors for delay were discovered is 71.4% or 930 cases: the incidence in which surgeries were delayed was 28.6% or 372 cases. 2. As results of logistic regression for delay, procedures involving women were delayed 1.4 times more frequently than those of men. Compared to Department A, Department B was 1.8 times more likely to be delayed, and Department H was 0.4 times less likely to be delayed. Regional anesthesia was 2.4 times more likely to be delayed than general anesthesia, and surgeries that PCA was applied were 0.6 times less likely to be delayed than those when it was not. Surgeries performed on the Thursday were 1.7 times more likely to be delayed than those performed on the Monday. Compared to surgeries performed between 07:00-07:59, those performed between 08:00-08:29 were 4.3 times higher. 3. The reasons for delay were related to surgeon, surgical department, patient, anesthesia, administrative system, sick ward, and support services. Among these, 5,755 minutes for 276 delayed cases could be resolved easily, and resolving delays of 3,320 minutes for 131 cases would be more difficult. Among the causes for delay that could be improved, delays due to patient's transfer and surgeon's factor were the most common, 21.6% and 17.4% respectively. 4. If resolvable delays are improved, pre-anesthesia room is administered, and regional anesthesia and PCA are done ahead of time, use of emergency operating rooms will increase, we can increase overall utilization by 4.09%, we will save 744 minutes a day, we can reduce the time the operation room is used after 4 PM by 35%, and we can resolve the operation cancellations due to insufficient operating rooms. For the increase in the use of operating rooms, we need to maximally decrease the delays that could be improved, by allocating block time based on used totals hours of elective cases, giving accurate information on surgery schedule, voluntary cooperation by staff participating in surgeries in reducing delay time, and the hospital management's will to improve delay.

• Proceedings of the KIEE Conference
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• 2000.07d
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• pp.3181-3183
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• 2000

As the fact that the simple data of text and sound in early year have been changed to be high quality images and sounds. PLL(Phase-Locked Loop) system plays an important role in communication system. VCO(Voltage Controlled Oscillator) is the most important part in PLL system because it can have critical effects on operation of PLL. Recently, it has been raised the necessity of high speed and high accuracy circuit application. In this paper, a new differential voltage clamped VCO using negative-skewed path is suggested. Using a dual-delay scheme to implement the VCO, higher operation frequency and wider tuning are achieved simultaneously. The dual-delay scheme means that both the negative skewed delay paths and the normal delay paths exist in the same ring oscillator. The negative skewed delay paths decrease the unit delay time of the ring oscillator below the single inverter delay time. As a result, higher operation frequency can be obtained. The whole characteristics of VCO are simulated by using HSPICE. Simulation results show that the resulting operating frequencies are 50% higher than those obtainable from the conventional approaches.

• Journal of Mechanical Science and Technology
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• v.16 no.12
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• pp.1643-1651
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• 2002

Magnetic levitation systems are required to have a large operating range in many applications. As one method to solve this problem, Time Delay Control (TDC) is applied to a single-axis magnetic levitation system in this paper A reduced-order observer is utilized to estimate states excluding measurable states in the control law. The system consists of a square air-core solenoid and a circular permanent magnet attached on a plastic ball. Theoretical magnetic forces of the system are obtained on the basis of the location of the magnet around the solenoid. The magnetic levitation force is obtained by the experiment, and then compared with the theoretical one. As the results of the control experiments, the nonlinear controller (TDC : 1-2 ㎜) has a larger operating range than the linear controller (PD control : 1-1.4 ㎜), and is superior to linear. control in the robustness to the modeling uncertainty and the performance of the disturbance rejection.

• Journal of Korean Society of Transportation
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• v.27 no.2
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• pp.199-206
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• 2009

In relation with economical efficiency analysis on investment evaluation of transportation system, among vehicle operating cost saving benefit that is applied to general preliminary assessment guidelines and investment evaluation guidelines, oil expense calculated data which concentrated and analyze on the relationship between oil consumption amount on running state and running speed. For uninterrupted flow which does not have stopped delay due to traffic signal, consideration for reduction benefit is possible due to the changes of running speed and travel time however, for interrupted flow which the stopping occurs due to signal control on actual signal intersection has no consideration for stopping delay time reduction and stopping rate improvement thus reflection of reality on improved effect analysis is difficult. Therefore, this research makes a framework to analyze benefits that reflects the features of signalized intersections by benefits associated with decrease of stopping delay time with existing research and developing vehicle operating cost calculation model formula. Vehicle operating cost has been redefined considering the stopping delay time by applying the oil consumption amount at idling and the economical benefit between conventional model and newly developed model when applied for the optimization of traffic signal system on the two roads in Seosan city has been analyzed comparative. While the importance of traffic system maintenance is being emphasized due to the increase of congested areas on roads, it is expected to assist in more realistic economical analysis which reflect the delay improvement through the presentation of an economic analysis model that considers the features of signalized intersections in signal optimization system improvements and effect analysis of congestion improvement projects`.

• 제어로봇시스템학회:학술대회논문집
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• 1994.10a
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• pp.140-145
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• 1994

In this paper, we consider a problem to estimate process parameters using input-output data collected from the process operating in closed-loop control system. When orders and delay-time of the process are known correctly, under some conditions of identifying experiments, it is reported that accurate identification results can be obtained by applying prediction error method. To get accurate estimates, it is necessary to know orders and delay-time of the process. It is difficult to determine them in closed-loop identification, because ill-condition for identification are easily caused by selection of unsuitable order or delay time. Furthermore, the procedures to select orders and delay-time in open-loop identification aren't always available in closed-loop identification. The purpose of this paper is to determine a delay-time under suitable assumption that order of the process are known as the first step.

• The Journal of the Korea institute of electronic communication sciences
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• v.9 no.9
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• pp.971-976
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• 2014

In this paper, we proposed a low power algorithm using state transition ready method. The proposed algorithm defined a sleep state, a idle state and a run state for the task. A state transition occurring at the time due to the delay time created in order to reduce the power consumption state in the middle of each inserted into the ready state. The ready state considering a power consumption and a delay time in state transition. A scheduling step of performing the steps in excess of the increasing problems have the delay time is long. The power consumption increased for the operation step increase. A state transition from a sleep state with the longest delay time in operating state occurs when the state is switched by the time delay caused by the increase in operating time reduces the overall power consumption reduced. Experiments [6] were compared with the results of the power consumption. The experimental results [6] is reduced power consumption than the efficiency of the algorithm has been demonstrated.

• Progress in Superconductivity
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• v.9 no.2
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• pp.157-161
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• 2008

Due to high speed operations and ultra low power consumptions RSFQ logic circuit is a very good candidate for future electronic device. The focus of the RSFQ circuit development has been on the advancement of analog-to-digital converters and microprocessors. Recent works on RSFQ ALU development showed the successful operation of an 1-bit block of ALU at 40 GHz. Recently, the study of an RSFQ analog-to-digital converter has been extended to the development of a single chip RF digital receiver. Compared to the voltage logic circuits, RSFQ circuits operate based on the pulse logic. This naturally leads the circuit structure of RSFQ circuit to be pipelined. Delay time on each pipelined stage determines the ultimate operating speed of the circuit. In simulations, a two junction Josephson transmission line's delay time was about 10 ps, a splitter's 14.5 ps, a switch's 13 ps, a half adder's 67 ps. Optimization of the 4-bit ALU circuit has been made with delay time consideration to operate comfortably at 10 GHz or above.