• Proceedings of the KIPE Conference
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• 2015.07a
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• pp.141-142
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• 2015

전기전자 기술발달에 따라 여러 가지 형태의 전기전자 부품이 많이 사용되고 있다. 이러한 전기전자 부품은 트랜지스터, Op Amp 등의 능동소자와 저항, 캐패시터, 리액터 등의 수동소자로 구분할 수 있다. 능동소자의 경우에는 사용용도에 따라 대부분 제조사에서 명확한 사양을 제공하지만, 수동소자의 경우는 명확한 사양을 제공하지 못하는 부품들도 있다. 정격범위를 명확히 제시하지 못하는 소자에 대표적으로 리액터가 있으며, 경우에 따라 정격에 미달하는 수준의 제품도 유통되고 있는 실정이다. 본 논문은 리액터 설계사양에 해당하는 철심의 자속밀도에 대한 실제 제품의 자속밀도포화 여부를 확인할 수 있는 기기의 동작설명과 그 실험결과를 제시한다.

• Proceedings of the KIEE Conference
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• 1994.11a
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• pp.382-384
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• 1994

Wireless communication has become a hot issue for its simplicity. Using light wave instead of micro wave has many advantages. It is simple to design a circuit because we can make a circuit with discrete components such as photo diode, photo detector, OP Amp[2]. And we can have many communication channels for we can use every frequency domain. In this paper, we design the wireless communication system and analyze the pulse signal. Then using ray tracing technology we simulate the distribution of light beam.

• Proceedings of the KIEE Conference
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• 2007.07a
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• pp.1862-1863
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• 2007

Testing the analog/mixed-signal circuitry of a mixed-signal IC has become a difficult task. Offset error, gain error, Non-monotonic behavior, Differential Non-linearity(DNL) error, Integral Non-linearity(INL) error are important specifications used as test parameters for DAC. In this paper, we propose an efficient BIST structure for DAC testing. The proposed BIST adds the circuit which uses the capacitor and op-amp, and accomplishes a test.

• Proceedings of the KIEE Conference
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• 1995.07a
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• pp.315-317
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• 1995

A simple drive circuit without position sensors for a switched reluctance motor is presented. The turn on and turn off points are determined by detecting the rate of change of the active phase current. The drive circuit consists of a current sensing resistor, RC filter, comparator, OP Amp, and OR gates. It is verified through the experiments that the switched reluctance motor with the proposed sensorless drive circuit is well operated in wide speed ranges.

• Journal of the Semiconductor & Display Technology
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• v.17 no.3
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• pp.104-107
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• 2018

In this paper, we developed a sensor for monitoring the leakage current through the chassis of the robot. The leakage current sensor needs to be developed because it is a necessary part to prevent electric shock accidents that may occur through the chassis of a robot or an electric vehicle. This leakage monitoring sensor was developed to be mounted directly on the chassis of the robot. This sensor protects the control system from noise by discharging static and high-frequency noise that may occur in the chassis of the robot and monitors the leakage current by measuring the amount of current discharged through the ground. In this paper, a leakage monitoring sensor was developed with a simple structure using resistors, capacitors and OP-AMP, and the performance was evaluated.

• Journal of Power Electronics
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• v.19 no.1
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• pp.34-43
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• 2019

An improved half-bridge LLC converter with a magamp auxiliary post-regulator is proposed in this paper. The function of the magamp is bypassed when the converter works within the low input-voltage range. Meanwhile, it operates as an auxiliary post-regulator when the input voltage is high. By changing the blocking time of the magamp, the dc gain of the converter can be extended. Hence, the input voltage range of the converter is extended. The realization of proposed topology does not require a complicated circuit. The controller of the magamp can be easily implemented using only passive components, transistors and an OP amp. The generalized operational principle is analyzed and the design criterion for the magamp is presented. Finally, a 25V output, 400W experimental prototype was built and tested for a 160-300V input-voltage range to verify the feasibility of the proposed method.

• Journal of Semiconductor Engineering
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• v.1 no.3
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• pp.81-87
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• 2020

An instrumentation amplifier (IA) and an analog-to-digital converter (ADC) are essential circuit blocks for accurate and robust sensor readout systems. This paper introduces recent advances in radiation-hardening by design (RHBD) techniques applied for the sensor readout integrated circuits (IC), e.g., the three-op-amp IA and the successive-approximation register (SAR) ADC, operating against total ionizing dose (TID) and singe event effect (SEE) in harsh radiation environments. The radiation-hardened IA utilized TID monitoring and adaptive reference control to compensate for transistor parameter variations due to radiation effects. The radiation-hardened SAR ADC adopts delay-based double-feedback flip-flops to prevent soft errors which flips the data bits. Radiation-hardened IA and ADC were verified through compact model simulation, and fabricated CMOS chips were measured in radiation facilities to confirm their radiation tolerance.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.17 no.7
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• pp.42-48
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• 2016

In this paper, a high-precision peak detector circuit that detects the output voltage information of a fly-back converter is proposed. The proposed design consists of basic analog elements with only one operational amplifier and three transistors. Because of its simple structure, the proposed circuit can minimize the delay time of the detection process, which has a strong impact on the precision of the regulation aspect of the fly-back converter. Furthermore, by using an amplifier and several transistors, the proposed detector can be fully integrated on-chip, instead of using discrete circuit elements, such as capacitors and diodes, as in conventional designs, which reduces the production cost of the fly-back converter module. In order to verify the performance of the proposed scheme, the peak detector was simulated and implemented by using a 0.35 m MagnaChip process. The gained results from the simulation with a sinusoidal stimulus signal show a very small detection error in the range of 0.3~3.1%, which is much lower than other reported detecting circuits. The measured results from the fabricated chip confirm the simulation results. As a result, the proposed peak detector is recommended for designs of high-performance fly-back converters in order to improve the poor regulation aspect seen in conventional designs.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.10
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• pp.57-63
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• 2014

This paper proposes an architecture of $3^{rd}$ order SDM(Sigma-Delta Modulator) with delayed feed-forward path in order to reduce the power consumption and area. The proposed SDM improve the architecture of conventional $3^{rd}$ order SDM which consists of two integrators. The proposed architecture can increase the coefficient values of first stage doubly by inserting the delayed feed-forward path. Accordingly, compared with the conventional architecture, the capacitor value($C_I$) of first integrator is reduced by half. Thus, because the load capacitance of first integrator became the half of original value, the output current of first op-amp is reduced as 51% and the capacitance area of first integrator is reduced as 48%. Therefore, the proposed method can optimize the power and the area. The proposed architecture in this paper is simulated under conditions which are supply voltage of 1.8V, input signal 1Vpp/1KHz, signal bandwidth of 24KHz and sampling frequency of 2.8224MHz in the 0.18um CMOS process. The simulation results are SNR(Signal to Noise Ratio) of 88.9dB and ENOB(Effective Number of Bits) of 14-bits. The total power consumption of the proposed SDM is $180{\mu}W$.

• Journal of IKEEE
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• v.22 no.4
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• pp.1025-1030
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• 2018

The proposed modulator is designed by utilizing a conventional structure employing time division technique to realize the 4th order delta-sigma modulator using one op-amp. In order to reduce the influence of KT/C noise, the capacitance in the first and second integrators reused was chosen to be 20pF and capacitance of third and fourth integrators was designed to be 1pF. The stage variable technique in the low power reconfigurable op-amp was used to solve the stability issue due to different capacitance loads for the reduction of KT/C noise. This technique enabled the proposed modulator to reduce the power consumption of 15% with respect to the conventional one. The proposed modulator was fabricated with 0.18um CMOS N-well 1 poly 6 metal process and consumes 305uW at supply voltage of 1.8V. The measurement results demonstrated that SNDR, ENOB, DR, FoM(Walden), and FoM(Schreier) were 66.3 dB, 10.6 bits, 83 dB, 98 pJ/step, and 142.8 dB at the sampling frequency of 256kHz, oversampling ratio of 128, clock frequency of 1.024 MHz, and input frequency of 250 Hz, respectively.