• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2003.11a
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• pp.53-58
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• 2003

The Wafer Level Packaging is one of the most important technologies in the semiconductor industry today. Its primary advantages are its small form factor and low cost potential for manufacturing including test procedure. The CASIO's WLP samples, application example and the structure are shown in Fig.1, 2&3. There are dielectric layer , under bump metal, re-distribution layer, copper post , encapsulation material and terminal solder .The key technologies are 'Electroplating thick copper process' and 'Unique wafer encapsulation process'. These are very effective in getting electrical and mechanical advantages of package. (Fig. 4). CASIO and CMK are developing a new System Packaging technology called the Embedded Wafer Level Package (EWLP) together. The active components (semiconductor chip) in the WLP structure are embedded into the Printed Wiring Board during their manufacturing process. This new technical approach has many advantages that can respond to requirements for future mobile products. The unique feature of this EWLP technology is that it doesn't contain any solder interconnection inside. In addition to improved electrical performance, EWLP can enable the improvement of module reliability. (Fig.5) The CASIO's WLP Technology will become the effective solution of 'KGD problem in System Packaging'. (Fig. 6) The EWLP sample shown in Fig.7 including three chips in the WLP form has almost same structure wi_th SoC's. Also, this module technology are suitable for RF and Analog system applications. (Fig. 8)

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.29 no.10
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• pp.758-765
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• 2018

This paper presents a 24-GHz frequency-modulated continuous wave(FMCW) radar transceiver with two Rx and one Tx channels in 65-nm complementary metal-oxide-semiconductor(CMOS) process and implemented it on a radar system using the developed transceiver chip. The transceiver chip includes a $14{\times}$ frequency multiplier, low-noise amplifier, down-conversion mixer, and power amplifier(PA). The transmitter achieves >10 dBm output power from 23.8 to 24.36 GHz and the phase noise is -97.3 GHz/Hz at a 1-MHz offset. The receiver achieves 25.2 dB conversion gain and output $P_{1dB}$ of -31.7 dBm. The transceiver consumes 295 mW of power and occupies an area of $1.63{\times}1.6mm^2$. The radar system is fabricated on a low-loss Duroid printed circuit board(PCB) stacked on the low-cost FR4 PCBs. The chip and antenna are placed on the Duroid PCB with interconnects and bias, gain blocks and FMCW signal-generating circuitry are mounted on the FR4 PCB. The transmit antenna is a $4{\times}4$ patch array with 14.76 dBi gain and receiving antennas are two $4{\times}2$ patch antennas with a gain of 11.77 dBi. The operation of the radar is evaluated and confirmed by detecting the range and azimuthal angle of the corner reflectors.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2000.10a
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• pp.463-467
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• 2000

In this paper, we have implemented the Web Server Patient Monitoring System using PPP. It is composed of two parts. The first part is the Analog board for acquiring ECG signals. The second part is the module for processing and transmitting the acquired signal. The second part is using PPP for dial-up networking, TCP/IP for Internet, HTTP for web browser and JAVA program for a Patient Monitoring Program in one chip. In home, it is not need to establish another network line because it uses a telephone line. And a user who want to monitor a patient's biosignal can monitor a patient without wholly open network because it is the network sewer. The Patient Monitoring Program runs on a web browser by downloaded JAVA codes when a user connect to this system. It can make the Home Patient Monitoring Program decrease cost. It can help to avoid the limitation of monitoring a patient.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.5C
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• pp.454-464
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• 2002

In the ATM-PON (Asynchronous Transfer Mode-Passive Optical Network), the downstream cell transmitted by an OLT is broadcast to all ONUs. The ONU receives selectively its own cells by VP filtering. On the other hand, the upstream cell can be transmitted by ONU in the case of receiving a grant from the OLT. After providing the grant to an ONU, the OLT expects the arrival of a cell after an elapse of the equalized round trip delay. ITU-T G.983.1 recommends that one bit error is allowed between the expected arrival time and the actual arrival time at the OLT. Because the ONU processes the different delay to each type of grant (ranging, user cell, and mimi-slot grant), it is not simple to design the transmission part of ONU. In this paper, we implement a grant processor which provides the delay accurately in the ONU TC chip with the FPGA. For the given equalized delay, it deals with the delay for the cell, the byte, and the bit unit by using the shift register, the byte counter, and the D flip-flop, respectively. We verify the operation of the grant processor by the time simulation and the measurement of the optical board output.

• Journal of the Korean Institute of Intelligent Systems
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• v.16 no.4
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• pp.485-492
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• 2006

This paper deals with implementation of network for distributed control system of a humanoid robot ISHURO(Inha Semyung Humanoid Robot). A humanoid robot needs much degree of freedom structurally and much data for having flexible movement. To realize such a humanoid robot, distributed control method is preferred to the centralized one since it gives a compactness, modularity and flexibility for the controllers. For organizing distributed control system of a humanoid robot, a control processor on a board is needed to individually control the joint motor and communication technology between the processors is required to transmit its information within control time. The processor is DSP-based processor and includes CAN network on a chip. It shares the computational load such as monitoring the sensor information and controlling the actuator between each of modules. In this paper, the communication architecture is suggested and its message protocol are discussed including message structure, time consumption for transmission, and controller structure at the view of distributed control for a humanoid robot. All of the sequence are simulated with Matlab and then verified with real walking experiment by ISHURO.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.14 no.1
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• pp.119-124
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• 2014

In this paper, A GSm/WCDMA band antenna which can be confirmed positioning information of a container by using the GPS/GLONASS bands on one board and can be sent the positioning information to the mobile communication network in real time is designed. A microstrip patch antennas which supports dual-band (GPS and GLONASS) was optimized. The antenna size is $25{\times}25{\times}5[mm]$. A chip monopole antennas which supports dual-band (GSM and WCDMA) was optimized. The antenna size is $27{\times}8{\times}3.2[mm]$. To amplify the Satellite reception signal level, two-stage low noise amplifier(LNA) was designed. The LNA gain is 27[dB]. The size of Jig for antennas measuring is $100{\times}30{\times}1[mm]$.

• Korean Parent-Child Health Journal
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• v.10 no.2
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• pp.147-157
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• 2007

Purpose: Assessment of stress and coping effort of hospitalized children's mother are very important factor to support and recover the children. The purpose of this study was to identify the stress and coping effort in mothers whose children are hospitalized. And analyzes the correlation between mother's stress and coping effort on the hospitalized children. Method: This study surveyed 70 mothers whose children are hospitalized. The data was collected for this study at one university hospital in Daejeon from June 1,2007 to July 10, 2007. The instruments used in this study were the mother's stress scale which was developed by Ok-Nam, You(1998), modified by Ho-Jin, Mun(2001), and the mother's coping effort were measured with the Coping Health Inventory for Parents(CHIP) developed by McCubbin and Patterson(1981). The data was analyzed by using SPSS program and include ANOVA, and Pearson's Correlation. Result: The mother's stress was average 2.42 out of a possible 4 points. Type of coping effort was in order of type III(cope with it by understanding medical circumstances)(M=2.73), type I(Cope with it through positive definition)(M=2.43), type II (cope with it by maintaining psychological stability)(M=2.28). Total coping effort according to general character of mothers whose children are hospitalized showed a significant difference in occupation(P<.05). Correlations between mother's stress and total coping effort was r=-.361(P<.05). Conclusion: This study based on nursing of stress and coping effort of hospitalized children's mothers. Pediatric nurses need to establish a stronger communication board and a relationship between medical staff and children's parents so that have supportive information. And to establish a support program that strengthens the coping effort of hospitalized children's mothers.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.5C
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• pp.371-381
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• 2005

In this paper, we propose an advanced hardware architecture for the CAVLC entropy encoder/decoder engine for real time video compression. The CAVLC (Context-based Adaptive Variable Length Coding) is a lossless compression method in H.264/AVC and it has high compression efficiency but has computational complexity. The reference memory size is optimized using partitioned storing method and memory reuse method which are based on partiality of memory referencing. We choose the hardware architecture which has the most suitable one in several encoder/decoder architectures for the mobile devices and improve its performance using parallel processing. The proposed architecture has been verified by ARM-interfaced emulation board using Altera Excalibur and also synthesized on Samsung 0.18 um CMOS technology. The synthesis result shows that the encoder can process about 300 CIF frames/s at 150MHz and the decoder can process about 250 CIF frames/s at 140Mhz. The hardware architectures are being used as core modules when implementing a complete H.264/AVC video encoder/decoder chip for real-time multimedia application.

• The KIPS Transactions:PartA
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• v.9A no.1
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• pp.1-8
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• 2002

Most of the traditional embedded web server systems have been designed for monitoring and controlling some dedicated equipments. Hence, not only they have no generality and flexibility but also they are too expensive for the lower-cost domestic equipment. To cope with these difficulty, we suggest a lower-cost ${\mu}$-embedded web server model which is suitable for monitoring and controlling the industry or house equipments by using the internet. The suggested model is based on an one-chip ${\mu}$-processor in which the ISP (In-System Programming) function and flash ROM are embedded basically to minimize the cost of H/W and S/W. Also it allows to add an new function dynamically to provide the generality and flexibility. Finally, to evaluate the feasibility of the suggested model, we have manufactured a test-board based on the ATMega103 ${\mu}$-processor and programmed the control program and tested it on the MS Explorer 5.0 environment.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2006.06a
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• pp.242-242
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• 2006

Increasingly complex tasks are performed by computers or cellular phone, requiring more and more memory capacity as well as faster and faster processing speeds. This leads to a constant need to develop more highly integrated circuit systems. Therefore, there have been numerous studies by many engineers investigating circuit patterning. In particular, PCB including module/package substrates such as FCB (Flip Chip Board) has been developed toward being low profile, low power and multi-functionalized due to the demands on miniaturization, increasing functional density of the boards and higher performances of the electric devices. Imprint lithography have received significant attention due to an alternative technology for photolithography on such devices. The imprint technique. is one of promising candidates, especially due to the fact that the expected resolution limits are far beyond the requirements of the PCB industry in the near future. For applying imprint lithography to FCB, it is very important to control thermal properties and mechanical properties of dielectric materials. These properties are very dependent on epoxy resin, curing agent, accelerator, filler and curing degree(%) of dielectric materials. In this work, the epoxy composites filled with silica fillers and cured with various accelerators having various curing degree(%) were prepared. The characterization of the thermal and mechanical properties wasperformed by thermal mechanical analysis (TMA), thermogravimetric analysis (TGA), differential scanning calorimetry (DSC), rheometer, an universal test machine (UTM).