• Journal of the Korean Wood Science and Technology
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• 제15권3호
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• pp.44-55
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• 1987

In order to study the effect of sawdustboard combined with plastic chips, 0.5mm($T_1$), 1mm($T_2$), 1.4mm($T_3$) thick nylon fiber. polypropylene rope fiber(RP), and 0.23mm thick moth-proof polypropylene net fiber(NP) were cut into 0.5, 1, 2cm long plastic chips. Thereafter, sawdustboard combined with plastic chips prepared as the above and plastic non-combined sawdustboard(control) were manufactured into 3 types of one-, two-, and three layer with 5 or 10% combination level. By the discussions and results at this study, the significant conclusions of mechanical and physical properties were summarized as follows: 1. The MORs were shown in the order of 3 layer> 2 layer> 1 layer among plastic non-combined boards, and $T_3$ < $T_2$ < $T_1$ < RP (NP(5%) < NP(l0%) among plastic combined boards. In 2cm long plastic chip in 1 layer board, the highest strength through all the composition was recognized. 1 layer board showing the lower strength with 0.5cm plastic chip rendered to the bending strength improvement by 2 or 3 layer board composition. On the other hand, 2 or 3 layer combined with 1, 2cm long polypropylene net fiber chips incurred MOR's conspicuous decrease requiring optimum plastic chip combined level and consideration to combined type. 2. MOE in plastic non-combined 3 layer board exhibited sandwich construction effect by higher resin content application to surface layer in the order of 3layer>1layer>2layer with the highest stiffness of the board combined with polypropylene chip, while nylon chip-combined board had little difference from plastic non-combined board. In relevant to length and layer effect, 3 layer board combined with the 0.5cm long polypropylene net fiber chip in 5% and 10% combined level presented 34-43% and 44-76% stiffness increase against plastic non-combined board(control), respectively. Moreover, in 1 layer board, 30% stiffness increase with 10% against 5% combined level in the 1 and 2cm long polypropylene net fiber chip was obtained. 3. Stress at proportional limit(Spl) showing the fiber relationship (r: 0.81-0.97) between MOR presented in the order of 1 layer<2 layer<3 layer in plastic non-combined board. Correspondingly, combined effect by layer and plastic chip length was similar to MOR's. 4. Differently from previous properties(MOR, MOE, Spl). work to maximum load(Wml) of 2 layer board approached to that of 3 layer board. Conforming the above phenomenon. 2 layer combined with 0.5cm long polypropylene net fiber chip kept the greater work than 1 layer. The polypropylene combined board superior to nylon -and plastic non - combined board seemed to have greater anti - failing capacity. 5. Internal bond strength(IB), in contrast to MOR's tendency. showed in the order of T1

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2000년도 제13회 신호처리 합동 학술대회 논문집
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• pp.105-108
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• 2000

CTI[1]의 응용 영역 중에서 인터넷 폰이 최근 뜨거운 관심의 대상으로 떠오르고 있다. 인터넷을 이용한 음성전달 기술은 인터넷의 성장 보급과 더불어 나날이발전 하고 있는데, 이러한 음성전달기술을 이용해 개발된 소프트 웨어를 통칭해서 인터넷 폰이라고 부르고 있다. 이러한 변화 속에서 비용의 절감과 비디오 전화, 영상회의와 같은 응용에 적용할 수 있는, 본 개발은 One Encoder One Decoder 지원의 VoIP(Voice over Internet Protocol) Phone에 관한 것으로, 특히 압축하여 인터넷 망에 접속시켜 사용할 수 있는 PC 장착형 One Board 형태의 시스템을 구현하였다. 이 Board에 사용 된 칩셋은 국내 회사인 C&S Technology 사의SEAGUL723이며, PC인터페이스는 PCI(Peripheral Component Interconnect) 버스 방식을 이용하였다. 주요 연구내용에 있어서 하드웨어 부분은 내선제어모듈,PCI 모듈, 칩셋을 이용한 음성신호처리 모듈, Board제어 모듈 등이 있으며, 소프트 웨어 설계 부분에 있어서는 하드웨어 구동을 위한 시스템 드라이브, Application과 인터넷 상의 VoIP 통신을 위한 소프트웨어, 사용자를 위한 User Interface 소프트 웨어 등이 있다.

• 동력기계공학회지
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• 제14권1호
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• pp.65-70
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• 2010

Magnetic levitation system is nonlinear and inherently unstable, so it is difficult to control. Analog control circuit was widly used as the controller of magnetic levitation system, but digital controller is now substituted for analog controller according to development of digital electronics. In this study, Atmel AVR series, ATmega 128 which is a kind of $\mu$-processor for digital controller is used because the chip is cheap and popular. We designed and made ATmega 128 one-board controller and aimed to verify validity through the experiance of levitation response.

• 한국생산제조학회지
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• 제20권5호
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• pp.559-563
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• 2011

Drop impact reliability assessment of solder joints on the flip chip is one of the critical issues for micro system packaging. Our previous researches have been showing that new solder ball compositions of Sn-3.0Ag-0.5Cu has better mechanical reliability than Sn-1.0Ag-0.5Cu. In this paper, dynamic reliability analysis using Finite Element Analysis (FEA) is carried out to assess the factors affecting flip chip in drop simulation. The design parameters are size and thickness of chip, and size, pitch and array of solder ball with composition of Sn1.0Ag0.5Cu. The board systems by JEDEC standard including 15 chips, solder balls and PCB are modeled with various design parameter combinations, and through these simulations, maximum yield stress and strain at each chip are shown at the solder balls. It is found that larger chip size, smaller chip array, smaller ball diameter, larger pitch, and larger chip thickness have bad effect on maximum yield stress and strain at solder ball of each chip.

• Journal of the Korean Wood Science and Technology
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• 제16권2호
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• pp.1-41
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• 1988

톱밥을 보드에 활용(活用)하기 위한 방안(方案)으로서, 톱밥자체의 약(弱)한 결집력(結集力)과 치수불량성(不良性)을 개선(改善)하기 위하여 비(非) 목질계(木質系) 재료(材料)인 폴리프로필렌 사(絲)칩과 배향사(配向絲)를 혼합(混合) 결체(結締)함에 다른 보드의 기초성질(基礎性質)로서 물리적(物理的) 기계적(機械的) 성질(性質)을 고찰(考察)하였는 바, 현재(現在) 제재용(製材用)으로 많이 이용(利用)되고 있는 나왕재(羅王材)(white meranti)의 톱밥에 개질재료(改質材料)로서 비(非) 목질(木質) 계(系) 플라스틱 물질(物質)인 폴리프로필렌 사(絲)를 칩상(狀) 또는 배향사(配向絲)의 형태(形態)로 조제(調製)하여 일반(一般) 성형법(成型法)을 적용(適用)함으로써 톱밥과 결체(結締) 구성(構成)한 톱밥보드를 제조(製造)하였다. 12 및 15%로 하여 구성(構成)하였다. 배향사(配向絲)는 보드폭방향(幅方向)으로 0.5, 1.0 및 1.5cm의 일정(一定)한 간격(間隔)으로 배열(配列)하였다. 위의 조건(條件)에 의(依)해 단(單) 2 3층(層)으로 각기(各己) 구분(區分)제조된 사(絲)칩 또는 배향사(配向絲) 구성(構成) 톱밥보드의 물리적(物理的) 및 기계적(機械的) 성질(性質)을 구명(究明)하였는 바, 그 주요(主要)한 결론(結論)을 요약(要約)하면 다음과 같다. 1. 사(絲)칩 혼합(混合) 단층구성(單層構成)보드의 두께 팽창율(膨脹率)은 톱잡대조(對照)보드의 팽창율보다 모두 낮았다. 사(絲)칩 함량(含量)을 증가(增加) 시킴에 따라서 두께 팽창율은 점차(漸次) 감소(減少)하는 경향이 뚜렷하였다. 한편, 2층구성(層構成)보드는 단층(單層) 구성(構成)보드보다 높은 팽창율을 나타냈으나 대부분이 톱밥대조(對照)보드 보다 팽창율이 낮았다. 3층(層)으로 사(絲)칩구성(構成)한 보드는 톱밥대조(對照)보드보다도 모두 낮은 두께 팽창율을 나타냈다. 2. 사(絲)칩 배향사(配向絲) 구성(構成)보드의 두께 팽창율은 0.5cm 배향간격에서 사(絲)칩함량(含量) 12%와 15%의 길이 1.0cm와 1.5cm로 구성함으로써 단층(單層) 및 3층구성(層構成)보드의 최저치(最低値)보다 더 낮았다. 3. 단층구성(單層構成)보드의 휨강도는 비중(比重) 0.51 구성(構成)보드의 경우 사(絲)칩함량(含量) 3%에서 톱밥대조)對照)보드보다 높은 강도를 나타냈으나, KS F 3104 의 파티클보드 100타입 기준(基準) 값인 80 kgf/$cm^2$에 훨씬 못 미쳤다. 그러나 비중(比重) 0.63 구성(構成)보드에서 함량(含量) 6%의 길이 1.5cm 사(絲)칩 구성과 함량(含量)3% 의 모든 사(絲)칩 길이로 구성한 보드, 그리고 비중(比重) 0.72의 모든 사(絲)칩 구성보드는 KS F 기준값을 훨씬 상회(上廻) 하였다. 2층구성(層構成)보드의 휨강도는 톱밥대조(對照)보드보다도 사(絲)칩구성의 경우 모두 낮았으며 단층구성(單層構成)보드의 휨강도보다도 낮은 값을 나타냈다. 3층구성(層構成)보드의 휨강도는 사(絲)칩 함량(含量) 9% 이하(以下)의 길이 1.5cm 구성보드는 모두 톱밥대조(對照)보드보다 높은 값을 나타냈으며 KSF 기준값을 훨씬 상회(上廻) 하였다. 4. 배향사구성(配向絲構成) 톱밥보드의 경우(境遇), 배향간격(配向間隔)이 좁은 0.5cm에서 가장 높은 휨강도를 나타냈으며, 배향간격이 보다 넓은 1.0cm 와 1.5cm 구성(構成)에서는 휨 강도가 0.5cm 간격 보다 낮았다. 그러나 배향사구성(配向絲構成) 톱밥보드는 모두 톱밥대조(對照)보드 보다 높은 휨강도를 나타냈다. 5. 사(絲칩) 배향사(配向絲) 구성 보드의 휨강도는 거의 대부분(大部分)의 구성보드에서 톱밥대조(對照)보드보다 높은 값을 나타냈으며 KSF 기준값을 훨씬 상회(上廻) 하였다. 특(特)히 배향간격이 좁고, 길이가 긴 사(絲)칩으로 구성한 보드의 휨강도가 높은 값을 나타냈다. 그리고 사(絲)칩을 배향사(配向絲)와 혼합(混合) 구성(構成)할 때 배향사의 간격이 넓어짐에 따라 톱밥과 배향사(配向絲)만으로 구성한 보드보다도 휨 강도가 높아지는 현상(現象)이 나타났다. 6. 단층(單層), 2층(層) 및 3층(層) 구성(構成) 보드의 탄성계수는 대부분(大部分) 톱밥대조(對照)보드 보다 낮은 값을 나타냈다. 그러나 배향사(配向絲) 구성(構成) 톱밥보드에 있어서는, 배향 간격이 0.5, 1.0, 1.5crn로 됨에 따라서 톱밥대조(對照)보드보다도 각각(各各) 20%, 18%, 10% 탄성계수가 증가(增加)되었다. 7. 사(絲)칩 배향사(配向絲) 구성(構成) 보드의 탄성계수(彈性係數)는 배향간격 0.5crn, 1.0cm 및 1.5crn에서 거의 모두 톱밥대조(對照)보드보드보다도 훨씬 높은 값을 나타냈다. 그리고 함량(含量)9% 이하(以下)에서 사(絲)칩길이를 0.5cm이상(以上)으로 구성하였을 때 배향사(配向絲)만을 구성한 톱밥보드보다도 탄성계수가 높아지는 현상(現象)이 나타났는데, 배향(配向)간격이 좁은 경우 사(絲)칩결체(結締)에 의(依)한 탄성계수(彈性係數) 증가효과(增加效果)가 컸다. 8. 사(絲)칩 혼합(混合) 단층구성(單層構成) 보드의 박리저항(剝離抵抗)은 톱밥대조(對照)보드 보다 모두 낮았다. 그러나 비중(比重) 0.63의 사(絲)칩 구성보드는 KS F 3104의 100타입 기준 값인 1.5kgf/$cm^2$를 모두 상회(上廻) 하였고, 비중(比重) 0.72의 사(絲)칩 구성보드는 200타입의 기준값 3kgf/$cm^2$를 상회(上廻)하는 박리저항(剝離抵抗)을 나타냈다. 2층(層), 3층(層) 및 배향구성(配向構成)도 거의 모두 200타입의 기준값 3kgf/$cm^2$를 상회(上廻) 하였다. 9. 단층구성(單層構成)보드의 나사못유지력(維持力)은 사(絲)칩을 혼합 구성한 경우, 대체(大體)로 톱밥대조(對照)보드보다도 낮은 값을 나타냈다. 그러나, 2층(層) 및 3층구성(層構成)보드에서는 사(絲)칩 구성(構成)에 따른 감소경향(減少傾向)이 나타나지 않고 대체로 고른 나사못 유지력을 나타냈다. 또한, 사(絲)칩 배향사(配向絲) 구성(構成)보드에서는 사(絲)칩함량(含量) 9% 이하(以下)에서 거의 모두 톱밥대조(對照)보드 보다도 높은 나사못 유지력을 나타냈다.

• 전기학회논문지
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• 제58권1호
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• pp.107-112
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• 2009

This paper describes design and fabrication issues of the SiP(System in Package) one-chip for a portable digital broadcasting receiver. It includes RF tuner chip, demodulator chip and passive components for the receiver system. When we apply the SiP one-chip technology to the broadcasting receiver, the system board size can be reduced from $776mm^2$ to $144mm^2$. SiP one-chip has an advantage that the area reduces more 81% than separated chips. Also the sensitivity performance advances -1dBm about 36 channels in the RF weak electric field, the power consumption reduces about 2mW and the C/N keeps on the same level.

• 한국지능시스템학회:학술대회논문집
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• 한국퍼지및지능시스템학회 1993년도 Fifth International Fuzzy Systems Association World Congress 93
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• pp.975-976
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• 1993

This talk presents the overview of the author's research and development activities on fuzzy inference hardware. We involved it with two distinct approaches. The first approach is to use application specific integrated circuits (ASIC) technology. The fuzzy inference method is directly implemented in silicon. The second approach, which is in its preliminary stage, is to use more conventional microprocessor architecture. Here, we use a quantitative technique used by designer of reduced instruction set computer (RISC) to modify an architecture of a microprocessor. In the ASIC approach, we implemented the most widely used fuzzy inference mechanism directly on silicon. The mechanism is beaded on a max-min compositional rule of inference, and Mandami's method of fuzzy implication. The two VLSI fuzzy inference chips are designed, fabricated, and fully tested. Both used a full-custom CMOS technology. The second and more claborate chip was designed at the University of North Carolina(U C) in cooperation with MCNC. Both VLSI chips had muliple datapaths for rule digital fuzzy inference chips had multiple datapaths for rule evaluation, and they executed multiple fuzzy if-then rules in parallel. The AT & T chip is the first digital fuzzy inference chip in the world. It ran with a 20 MHz clock cycle and achieved an approximately 80.000 Fuzzy Logical inferences Per Second (FLIPS). It stored and executed 16 fuzzy if-then rules. Since it was designed as a proof of concept prototype chip, it had minimal amount of peripheral logic for system integration. UNC/MCNC chip consists of 688,131 transistors of which 476,160 are used for RAM memory. It ran with a 10 MHz clock cycle. The chip has a 3-staged pipeline and initiates a computation of new inference every 64 cycle. This chip achieved an approximately 160,000 FLIPS. The new architecture have the following important improvements from the AT & T chip: Programmable rule set memory (RAM). On-chip fuzzification operation by a table lookup method. On-chip defuzzification operation by a centroid method. Reconfigurable architecture for processing two rule formats. RAM/datapath redundancy for higher yield It can store and execute 51 if-then rule of the following format: IF A and B and C and D Then Do E, and Then Do F. With this format, the chip takes four inputs and produces two outputs. By software reconfiguration, it can store and execute 102 if-then rules of the following simpler format using the same datapath: IF A and B Then Do E. With this format the chip takes two inputs and produces one outputs. We have built two VME-bus board systems based on this chip for Oak Ridge National Laboratory (ORNL). The board is now installed in a robot at ORNL. Researchers uses this board for experiment in autonomous robot navigation. The Fuzzy Logic system board places the Fuzzy chip into a VMEbus environment. High level C language functions hide the operational details of the board from the applications programme . The programmer treats rule memories and fuzzification function memories as local structures passed as parameters to the C functions. ASIC fuzzy inference hardware is extremely fast, but they are limited in generality. Many aspects of the design are limited or fixed. We have proposed to designing a are limited or fixed. We have proposed to designing a fuzzy information processor as an application specific processor using a quantitative approach. The quantitative approach was developed by RISC designers. In effect, we are interested in evaluating the effectiveness of a specialized RISC processor for fuzzy information processing. As the first step, we measured the possible speed-up of a fuzzy inference program based on if-then rules by an introduction of specialized instructions, i.e., min and max instructions. The minimum and maximum operations are heavily used in fuzzy logic applications as fuzzy intersection and union. We performed measurements using a MIPS R3000 as a base micropro essor. The initial result is encouraging. We can achieve as high as a 2.5 increase in inference speed if the R3000 had min and max instructions. Also, they are useful for speeding up other fuzzy operations such as bounded product and bounded sum. The embedded processor's main task is to control some device or process. It usually runs a single or a embedded processer to create an embedded processor for fuzzy control is very effective. Table I shows the measured speed of the inference by a MIPS R3000 microprocessor, a fictitious MIPS R3000 microprocessor with min and max instructions, and a UNC/MCNC ASIC fuzzy inference chip. The software that used on microprocessors is a simulator of the ASIC chip. The first row is the computation time in seconds of 6000 inferences using 51 rules where each fuzzy set is represented by an array of 64 elements. The second row is the time required to perform a single inference. The last row is the fuzzy logical inferences per second (FLIPS) measured for ach device. There is a large gap in run time between the ASIC and software approaches even if we resort to a specialized fuzzy microprocessor. As for design time and cost, these two approaches represent two extremes. An ASIC approach is extremely expensive. It is, therefore, an important research topic to design a specialized computing architecture for fuzzy applications that falls between these two extremes both in run time and design time/cost. TABLEI INFERENCE TIME BY 51 RULES {{{{Time }}{{MIPS R3000 }}{{ASIC }}{{Regular }}{{With min/mix }}{{6000 inference 1 inference FLIPS }}{{125s 20.8ms 48 }}{{49s 8.2ms 122 }}{{0.0038s 6.4㎲ 156,250 }} }}

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2008년도 하계학술대회 논문집 Vol.9
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• pp.10-10
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• 2008

Flip chip technology is keeping pace with the increasing connection density of the ICs and is capable of transferring semiconductor performance to the printed circuit board. One of the most general flip chip technology is CPB technology presented by Intel. The CPTB technology has similar benefits with CPB but has simpler process and better reliability characteristics. In this paper, process sequence and structure of CPTB are presented.

• 한국소음진동공학회논문집
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• 제21권8호
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• pp.768-773
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• 2011

This work presents an experimental investigation on vibration control of the active hybrid mount system for naval ships. To reduce unwanted vibrations, this paper proposes an active mount which consists of rubber element, piezostack actuator and inertial mass. The rubber element supports a mass. The piezostack actuator generates a proper control force and supply it to the mount system. To avoid being broken piezostack actuator, an actuator of the proposed mount is devised as an inertial type, in which a piezostack actuator is positioned between inertial mass and rubber element. Vibration control performances of the active mount system are evaluated via experiment. To attenuate the unwanted vibrations transferred from upper mass, the feedforward control is designed. In order to implement a control experiment, the active mount system supported by four active mounts is constructed. For realization of the controller, one-chip board is manufactured and utilized. Subsequently, vibration control performances of the proposed active mount system are experimentally evaluated in frequency domains.

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 1991년도 한국자동제어학술회의논문집(국내학술편); KOEX, Seoul; 22-24 Oct. 1991
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• pp.24-29
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• 1991

RCCL(Robot Control C Library) is general purpose robot control language. It is programmed with C language and composed of C library. So it is well portable and supports sensor integration control and high level force control algorithms. We implemented RCCL on PUMA. We developed servo controller of DDC(Direct Digital Control). We used intel 8097BH one chip micro controller as CPU. One digital servo board controls three motors. Host computer is IBM PC 386DX-33 with RCCL.