• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2008.10a
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• pp.100-103
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• 2008

In this paper, we propose H.264 Encoder integrating Intra Prediction, Deblocking filter, Context-Based Adaptive Variable Length Coding, and Motion Estimation encoder module. This designed module can be operated in 440 cycle for one-macroblock. To verify the Encoder architecture, we developed the reference C from JM 9.4 and verified the our developed hardware using test vector generated by reference C. The designed circuit can be operated in 166MHz clock system, and has 1800k gate counts using Charterd 0.18um process including SRAM memory. Manufactured chip has the size of $6{\times}6mm$ and 208 pins package.

• Journal of KIISE:Computer Systems and Theory
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• v.35 no.7
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• pp.354-360
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• 2008

Power-related issues have become important considerations in current generation microprocessor design. One of these issues is that of elevated on-chip temperatures. This has an adverse effect on cooling cost and, if not addressed suitably, on chip reliability. In this paper we investigate the general trade-offs between temporal and spatial hot spot mitigation schemes and thermal time constants, workload variations and microprocessor power distributions. By leveraging spatial and temporal heat slacks, our schemes enable lowering of on-chip unit temperatures by changing the workload in a timely manner with Operating System (OS) and existing hardware support.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2006.05a
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• pp.31-32
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• 2006

A signal conditioning circuit for capacitive sensors was developed using a commercial single chip solution. Since capacitive displacement sensors can achieve high resolution and linearity, they have been widely used as precision sensors within the range of several hundred micrometers. However, they inherently have a limitation in low frequency range and some nonlinearity characteristics and so a specially designed signal conditioning circuit is needed to handle these properties. Up to now, several companies already have succeeded in the development of the capacitive sensors system and they are commercially available in the market. In this research, to construct the signal processing circuits more easily and simply, we used a universal LVDT signal conditioner (AD698). Since the AD698 provides one chip solution for a basic signal processing including modulation and demodulation using various internal components, we can build the processing circuits successfully with minimal additional circuits: a compensation circuits for the drift caused by the bias current of OP amplifiers and a fine adjustment circuit for the elimination of nonlinearity. The signal processing circuits shows nonlinearity less than 0.05% in the comparison with a laser interferometer.

• Journal of Korean Society on Water Environment
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• v.23 no.1
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• pp.33-37
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• 2007

Microelectrodes for measuring nitrogenous compounds (${NH_4}^+$, ${NO_3}^-$) that were applied into the microfluidics chips was investigated, and the effect of temperature was especially examined. In this specific research, microelectrodes were first calibrated to check the function, and then microsensor that was combined microelectrode with microfluidic chip was re-calibrated. Experimental results showed that there are no change in the function between microelectrode and microfluidic chip. The electro motive force (EMF) for the ${NH_4}^+$ microsensor was similar to the one theoretically calculated from Nernst equation, but the EMF for ${NO_3}^-$ showed minor change.

• Journal of the Institute of Convergence Signal Processing
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• v.1 no.1
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• pp.89-96
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• 2000

In this paper, we propose a vision algorithm for the inspection of very small RF-chip inductor which is used in mobile-communication terminal. The proposed method divides coil part from the inductor body by local adaptive thresholding and integral projection method. After dividing work, the coil components are extracted by thinning and labelling techniques. The test items are the number of turns, the intervals in coil, and the measure of uniformity between the extracted lines. If the values of these are more than the specific value a tested product is decided bad one. In the simulation, the proposed method has a good performance.

• ETRI Journal
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• v.31 no.2
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• pp.111-120
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• 2009

Network-on-chip (NoC) architecture provides a highper-formance communication infrastructure for system-on-chip designs. Circuit-switched networks guarantee transmission latency and throughput; hence, they are suitable for NoC architecture with real-time traffic. In this paper, we propose an efficient integrated scheme which automatically maps application tasks onto NoC tiles, establishes communication circuits, and allocates a proper bandwidth for each circuit. Simulation results show that the average waiting times of packets in a switch in $6{\times}6$6, $8{\times}8$, and $10{\times}10$ mesh NoC networks are 0.59, 0.62, and 0.61, respectively. The latency of circuits is significantly decreased. Furthermore, the buffer of a switch in NoC only needs to accommodate the data of one time slot. The cost of the switch in the circuit-switched network can be reduced using our scheme. Our design provides an effective solution for a critical step in NoC design.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.13 no.12
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• pp.2647-2654
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• 2009

In this paper, we propose H.264 Encoder integrating Intra Prediction, Deblocking Filter, Context-Based Adaptive Variable Length Coding, and Motion Estimation encoder module. This designed module can be operated in 440 cycle for one-macroblock. To verify the Encoder architecture, we developed the reference C from JM 9.4 and verified the our developed hardware using test vector generated by reference C. The designed circuit can be operated in 166MHz clock system, and has 1800K gate counts using Charterd 0.18 um process including SRAM memory. Manufactured chip has the size of $6{\times}6mm$ and 208 pins package.

• Journal of the Semiconductor & Display Technology
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• v.20 no.3
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• pp.32-38
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• 2021

We developed an inductively coupled plasma (ICP) etcher for GaN etching using a parallel plasma electrode source with a multifunctional chuck matched to it in order for the low power consumption and low process cost in comparison with the conventional ICP system with a helical-type plasma electrode source. The optimization process condition using it for the micro light-emitting diode (µ-LED) chip fabrication was established, which is an ICP RF power of 300 W, a chuck power of 200 W, a BCl₃/Cl₂ gas ratio of 3:2. Under this condition, the mesa structure with the etch depth over 1 ㎛ and the etch angle over 75° and also with no etching residue was obtained for the µ-LED chip. The developed ICP showed the improved values on the process pressure, the etch selectivity, the etch depth uniformity, the etch angle profile and the substrate temperature uniformity in comparison with the commercial ICP. The µ-LED chip fabricated using the developed ICP showed the similar or improved characteristics in the L-I-V measurements compared with the one fabricated using the conventional ICP method

• Journal of IKEEE
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• v.27 no.1
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• pp.65-70
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• 2023

More than 10,000 Carbon NanoTube Field Effect Transistors (CNTFETs), which have advantages such as high carrier mobility, large saturation velocity, low intrinsic capacitance, flexibility, and transparency, have been successfully integrated into one semiconductor chip using conventional semiconductor design procedures and manufacturing processes. Three-dimensional multilayer structure of the CNTFET semiconductor chip and various CNTFET manufacturing process research increase the possibility of making the hybrid MOSFET-CNTFET semiconductor chip which combines conventional MOSFETs and CNTFETs together in a semiconductor chip. This paper discusses a methodology to design 6T binary SRAM using hybrid MOSFET-CNTFET. By utilizing the existing MOSFET SRAM or CNTFET SRAM design method, we will introduce a method of designing a hybrid MOSFET-CNTFET SRAM and compare its performance with the conventional MOSFET SRAM and CNTFET SRAM.

• International Journal of Highway Engineering
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• v.17 no.6
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• pp.47-54
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• 2015

PURPOSES : The objective of this study is to evaluate the early adhesive characteristic of asphalt emulsions, including polymer-modified emulsions, for chip seals using the surface energy concept, the bitumen bond strength (BBS) test, and the Vialit test. METHODS : Two general methods, the BBS test and Vialit test, were applied to investigate the bond strength and the aggregate loss, respectively. A new theory, the surface free energy (SFE) theory, was used to evaluate the adhesive characteristic between the emulsion and the aggregate. Based on the theory, the contact angles were measured, and then the surface energy components were calculated. Using those components, the work of adhesion (Wa) was calculated for each emulsion. To ensure reliable results, all the tests were performed under the same conditions, i.e., at $25^{\circ}C$ for 240 minutes of curing time. For the materials, three emulsions (CRS-2, CRS-2L, and CRS-2P) and one aggregate type (granite) were employed. RESULTS AND CONCLUSIONS : Under the same conditions, the modified emulsions showed better adhesive characteristics and curing behaviors than the unmodified emulsions. In addition, there was no significant difference between the various modified emulsions. One of the important findings is that the analysis by Wa presents more sensitive results than other methods. The results of the Wa showed that the CRS-2P emulsion has the best adhesive characteristics. Consequently, the use of modified emulsions for chip seals could prevent aggregate loss and allow open traffic earlier.