• 전기학회논문지P
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• 제61권1호
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• pp.47-54
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• 2012

This paper presents implementation of SVPWM technique for three phase Voltage Source Inverter using FPGA. Software-based vector-control calculations much this drawback, in order to improve the hardware-vector-control tries. Without the need for additional software, vector control algorithm is designed to be modular SOPC, and DSP will reduce most of the operations. In this paper, the SVPWM that using HDL for the AC motor vector control algorithm level, and the dead time part and the speed control in order to controled a speed detector and designed in the form of modules. Then ALTERA corporation Cyclone III series EP3C16F484 can be verified by implemented.

• 전기학회논문지
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• 제63권12호
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• pp.1710-1715
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• 2014

In this paper, we propose a novel on-chip test logic for TSV fault detection in 3-dimensional integrated circuits. The proposed logic called OTT realizes the input signal delay-based TSV test method introduced earlier. OTT only includes one F/F, two MUXs, and some additional logic for signal delay. Thus, it requires small silicon area suitable for TSV testing. Both pre-bond and post-bond TSV tests are able to use OTT for short or open fault as well as small delay fault detection.

• 한국분말야금학회:학술대회논문집
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• 한국분말야금학회 2006년도 Extended Abstracts of 2006 POWDER METALLURGY World Congress Part2
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• pp.969-970
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• 2006

In present work, manufacturing technologies of titanium hydride powder were studied for recycling of titanium tuning chip and for this, attrition ball milling was carried out under $H_2$ pressure of 0.5 MPa. Ti chips were completely transformed into $TiH_2$ within several hundred seconds. Dehydrogenation process $TiH_2$ powders is consist of two reactions: one is reaction of $TiH_2$ to $TiH_x$ and the other decomposition of $TiH_x$ to Ti and $H_2$. The former reaction shows relatively low activation energy and it is suggested that the reaction is caused by introduction of defects due to milling.

• 전기학회논문지
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• 제56권11호
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• pp.1982-1987
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• 2007

This paper presents the design and analysis of LNA-Mixer for 2.45GHz RFID reader. The LNA is implemented by PCSNIM method for low power consumption. The Mixer is implemented by using the Gilbert-type configuration, current bleeding technique and the resonating technique for the tail capacitance. The connection between the two designed circuits is made by active balun. This LNA-Mixer has about 22dB gain and 8.5dB Noise Figure for -50dBm input RF power, LO power is 0dBm, RF frequency is 2.45 GHz and IF frequency is 100kHz. The layout of LNA-Mixer for one-chip design in a 0.18-um TSMC process has $2.5mm{\times}1.0mm$ size.

• 전기학회논문지
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• 제65권12호
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• pp.2061-2068
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• 2016

A Bloom filter is a space-efficient data structure popularly applied in many network algorithms. This paper proposes a vectored Bloom filter to provide a high-speed Internet protocol (IP) address lookup. While each hash index for a Bloom filter indicates one bit, which is used to identify the membership of the input, each index of the proposed vectored Bloom filter indicates a vector which is used to represent the membership and the output port for the input. Hence the proposed Bloom filter can complete the IP address lookup without accessing an off-chip hash table for most cases. Simulation results show that with a reasonable sized Bloom filter that can be stored using an on-chip memory, an IP address lookup can be performed with less than 0.0003 off-chip accesses on average in our proposed architecture.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2009년도 9th International Meeting on Information Display
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• pp.49-49
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• 2009

Phosphors with oxide host material, YAG:$Ce^{3+}$ and $(Ca,Sr,Ba)_2SiO_4:Eu^{2+}$ yellow phosphor, has been used for LED applications. The WLEDs using these phosphors are widely used for LCD backlighting, automobile, and general lighting applications since they have high conversion efficiency and good thermal and chemical stability which can meet necessary life time of LED products up to now. With advances of LED chip technology, the external quantum efficiency and driving current in chip get higher so that the phosphors for high power chip are required to maintain high conversion efficiency and stability at high temperature due to the heat dissipated from LED chips. In addition, higher color rendering index of LED lighting and color reproducibility of LCD than those of LEDs with single yellow phosphors are required. In order to overcome these technical issues rising from evolution of LED technology, new phosphors are in demand and nitride phosphors, one of the promising new candidate materials, will be discussed here.

• 대한기계학회논문집
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• 제19권11호
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• pp.3072-3083
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• 1995

The numerical simulation on the three-dimensional natural convection heat transfer in the enclosure with heat generating chip is performed, and the effects of convective heat loss and vents are also examined. The effects of the Rayleigh number and outer Nusselt number (Nu$_{0}$) on the maximum chip temperature and the fractions of heat loss from the hot surfaces are investigated. The results show that conduction through the substrate is dominant in heat dissipation. With the increase of Rayleigh number, heat dissipation through the chip surfaces increases and heat loss through the substrate decreases. Maximum dimensionless temperature with vents is found to decrease about 40% compared to the one without vents at Nu$_{0}$=0.l. It is also shown that effects of size and location of the vents are negligible.ble.

• ETRI Journal
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• 제26권1호
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• pp.1-6
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• 2004

The photonic quantum ring (PQR) laser is a three dimensional whispering gallery (WG) mode laser and has anomalous quantum wire properties, such as microampere to nanoampere range threshold currents and ${\sqrt{T}}$-dependent thermal red shifts. We observed uniform bottom emissions from a 1-kb smart pixel chip of a $32{\times}32$ InGaAs PQR laser array flip-chip bonded to a 0.35 ${\mu}m$ CMOS-based PQR laser driver. The PQR-CMOS smart pixel array, now operating at 30 MHz, will be improved to the GHz frequency range through device and circuit optimization.

• ETRI Journal
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• 제36권4호
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• pp.643-653
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• 2014

To reduce interconnect delay and power consumption while improving chip performance, a three-dimensional integrated circuit (3D IC) has been developed with die-stacking and through-silicon via (TSV) techniques. The power supply problem is one of the essential challenges in 3D IC design because IR-drop caused by insufficient supply voltage in a 3D chip reduces the chip performance. In particular, power bumps and TSVs are placed to minimize IR-drop in a 3D power delivery network. In this paper, we propose a design methodology for 3D power delivery networks to minimize the number of power bumps and TSVs with optimum mesh structure and distribute voltage variation more uniformly by shifting the locations of power bumps and TSVs while satisfying IR-drop constraint. Simulation results show that our method can reduce the voltage variation by 29.7% on average while reducing the number of power bumps and TSVs by 76.2% and 15.4%, respectively.

• JSTS:Journal of Semiconductor Technology and Science
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• 제10권1호
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• pp.28-36
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• 2010

Hardware implementation methods for Artificial Neural Network (ANN) have been researched for a long time to achieve high performance. We have proposed a Network on Chip (NoC) for ANN, and this architecture can reduce communication load and increase performance when an implemented ANN is small. In this paper, a multiple NoC models are proposed for ANN, which can implement both a small size ANN and a large size one. The simulation result shows that the proposed multiple NoC models can reduce communication load, increase system performance of connection-per-second (CPS), and reduce system running time compared with the existing hardware ANN. Furthermore, this architecture is reconfigurable and reparable. It can be used to implement different applications of ANN.