• Title/Summary/Keyword: One-chip

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Measuring Circuit Design of RI-Gauge for Compaction Control (성토시공관리용 방사성 동위원소 이용계기의 측정회로설계)

  • Kil, Gyung-Suk;Song, Jae-Yong;Kim, Ki-Joon;Whang, Joo-Ho;Song, Jung-Ho
    • Journal of Sensor Science and Technology
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    • v.6 no.5
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    • pp.385-391
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    • 1997
  • An objection of this study is to develop a measuring circuit of a gauge using radioisotope for compaction control. The gauge developed in this study makes use of radioisotope with the activity exempted from domestic atomic law and consists of measuring circuits for gamma-rays and thermal neutrons, a high voltage supply unit, and a microprocessor. To obtain meaningful numbers of pulse counts, parallel five and two circuits are provided for gamma-rays and thermal neutrons, respectively. Being simple in electrical characteristics of G-M detector for gamma-rays, pulses are counted through only a shaping circuit. Very small pulses generated from He- 3 proportional detector for thermal neutrons are amplified to the maximum of 50 [dB] and a window comparator accepts only pulses with meaning. To minimize effects of natural environmental radiation and electrical noise, circuits are electrostatically shielded and pulses made by ripples are eliminated by taking frequency of high voltage supplied to the circuit and pulse height of ripples into consideration. One-chip microprocessor is applied to process various counts, results are stored and the gauage is made capable to communicate with PC. Enough and meaningful numbers of pulses are counted with the prototype gauage for compaction control.

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Design of PMOS-Diode Type eFuse OTP Memory IP (PMOS-다이오드 형태의 eFuse OTP IP 설계)

  • Kim, Young-Hee;Jin, Hongzhou;Ha, Yoon-Gyu;Ha, Pan-Bong
    • The Journal of Korea Institute of Information, Electronics, and Communication Technology
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    • v.13 no.1
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    • pp.64-71
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    • 2020
  • eFuse OTP memory IP is required to trim the analog circuit of the gate driving chip of the power semiconductor device. Conventional NMOS diode-type eFuse OTP memory cells have a small cell size, but require one more deep N-well (DNW) mask. In this paper, we propose a small PMOS-diode type eFuse OTP memory cell without the need for additional processing in the CMOS process. The proposed PMOS-diode type eFuse OTP memory cell is composed of a PMOS transistor formed in the N-WELL and an eFuse link, which is a memory element and uses a pn junction diode parasitic in the PMOS transistor. A core driving circuit for driving the array of PMOS diode-type eFuse memory cells is proposed, and the SPICE simulation results show that the proposed core circuit can be used to sense post-program resistance of 61㏀. The layout sizes of PMOS-diode type eFuse OTP memory cell and 512b eFuse OTP memory IP designed using 0.13㎛ BCD process are 3.475㎛ × 4.21㎛ (= 14.62975㎛2) and 119.315㎛ × 341.95㎛ (= 0.0408mm2), respectively. After testing at the wafer level, it was confirmed that it was normally programmed.

Nutritional Knowledge and Eating Behavior of High School Students in Sungnam Area (남.여 중고등학생의 식생활 행동과 영양지식에 대한 실태 연구 (성남 지역을 중심으로))

  • Lee, Young-Mee;Han, Myung-Sook
    • Journal of the Korean Society of Food Culture
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    • v.11 no.3
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    • pp.305-316
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    • 1996
  • The purpose of this study was to find out how much they have several aspects of food related knowledge and eating behaviors of high school students in Sungnam area. The self-administrated questionnaire was used. The result were as follows: 1. The average height of boys and girls was $172.6{\pm}0.7$ cm and $156.3{\pm}1.5$ cm respectively. The average weights of them were $62.4{\pm}0.5$ kg (male) and $47.2{\pm}0.8$ kg (female). BMI (Body Mass Index) of them were $20.74{\pm}0.14$ (male), $18.82{\pm}0.28$ (female). The average age is 16.7 years old. 2. The 66.5% of the subjects were spent more than one-third of their pocket money in buying on light meals during three times a week. There were significant differences between income level of family. Boys spent more money on each meal than girls. And significant differences were also obserbed by their residence area and Bundang residences spent more in buying snacks. 3. The rate of skipping meals was 51.2% in boys compared with 68.0% in girls. The frequencies of buying snacks instead of main meal were high in girls. Time limits in eating may possibly be the main reason for skipping meals (59.8%), especially in the morning. Skipping a breakfast becomes general eating habits in high school students, because of pressure for time to go to school. 4. It is required that parents should be taught to prepare balanced lunch box for their children because the rate of students who prepared two lunch boxes are 49.4%. 5. The students took snacks once or twice a day. They usually bought snacks in school concessions (51.8%) and they selected items of snack instinctivly. The girls ate snacks during lunch break time (31.7%) and after dinner (23.6%). Boys ate snacks after dinner (29.1%). Preference of foods were different by sex. Boys preferred bread (31.7%), milk and otherdairy products (80.8%), cola and soda (42.0%) as their snacks between meals. Girls selected biscuit, chip, beverage, coffee as their snacks, frequently. 6. BMI value of the group who ate between meals more than three times a day was lower $(18.78{\pm}0.65)$ than that of the group who ate nothing between meals $(20.71{\pm}3.79)$. 7. As for the nutritional knowledge, the students generally had higher correct rate of answer about which nutritive components of food has (76.6%). But they had lower knowledge on questions of nutritive values in food (10.6%). There was a meaningful relation between favorite food and nutritional knowledge. In conclusion, there were some problems on nutritional knowledge and eating habits among the high school students. Therefore, it was required that girls should be learned to recognize the importance of breakfast and needed to select balanced meals and snacks. And it was required that the nutrition education should be complemented to motivate and improve practical eating behaviors.

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Enhanced and Practical Alignment Method for Differential Power Analysis (차분 전력 분석 공격을 위한 향상되고 실제적인 신호 정렬 방법)

  • Park, Jea-Hoon;Moon, Sang-Jae;Ha, Jae-Cheol;Lee, Hoon-Jae
    • Journal of the Korea Institute of Information Security & Cryptology
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    • v.18 no.5
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    • pp.93-101
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    • 2008
  • Side channel attacks are well known as one of the most powerful physical attacks against low-power cryptographic devices and do not take into account of the target's theoretical security. As an important succeeding factor in side channel attacks (specifically in DPAs), exact time-axis alignment methods are used to overcome misalignments caused by trigger jittering, noise and even some countermeasures intentionally applied to defend against side channel attacks such as random clock generation. However, the currently existing alignment methods consider only on the position of signals on time-axis, which is ineffective for certain countermeasures based on time-axis misalignments. This paper proposes a new signal alignment method based on interpolation and decimation techniques. Our proposal can align the size as well as the signals' position on time-axis. The validity of our proposed method is then evaluated experimentally with a smart card chip, and the results demonstrated that the proposed method is more efficient than the existing alignment methods.

A Study on the Improvement of Tool's Life by Applying DLC Sacrificial Layer on Nitride Hard Coated Drill Tools (드릴공구의 이종질화막상 DLC 희생층 적용을 통한 공구 수명 개선 연구)

  • Kang, Yong-Jin;Kim, Do Hyun;Jang, Young-Jun;Kim, Jongkuk
    • Journal of the Korean institute of surface engineering
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    • v.53 no.6
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    • pp.271-279
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    • 2020
  • Non-ferrous metals, widely used in the mechanical industry, are difficult to machine, particularly by drilling and tapping. Since non-ferrous metals have a strong tendency to adhere to the cutting tool, the tool life is greatly deteriorated. Diamond-like carbon (DLC) is one of the promising candidates to improve the performance and life of cutting tool due to their low frictional property. In this study, a sacrificial DLC layer is applied on the hard nitride coated drill tool to improve the durability. The DLC coatings are fabricated by controlling the acceleration voltage of the linear ion source in the range of 0.6~1.8 kV. As a result, the optimized hardness(20 GPa) and wear resistance(1.4 x 10-8 ㎣/N·m) were obtained at the 1.4 kV. Then, the optimized DLC coating is applied as an sacrificial layer on the hard nitride coating to evaluate the performance and life of cutting tool. The Vickers hardness of the composite coatings were similar to those of the nitride coatings (AlCrN, AlTiSiN), but the friction coefficients were significantly reduced to 0.13 compared to 0.63 of nitride coatings. The drilling test were performed on S55C plate using a drilling machine at rotation speed of 2,500 rpm and penetration rate of 0.25 m/rev. The result showed that the wear width of the composite coated drills were 200 % lower than those of the AlCrN, AlTiSiN coated drills. In addition, the cutting forces of the composite coated drills were 13 and 15 % lower than that of AlCrN, AlTiSiN coated drills, respectively, as it reduced the aluminum clogging. Finally, the application of the DLC sacrificial layer prevents initial chipping through its low friction property and improves drilling quality with efficient chip removal.

Design of Single Power CMOS Beta Ray Sensor Reducing Capacitive Coupling Noise (커패시터 커플링 노이즈를 줄인 단일 전원 CMOS 베타선 센서 회로 설계)

  • Jin, HongZhou;Cha, JinSol;Hwang, ChangYoon;Lee, DongHyeon;Salman, R.M.;Park, Kyunghwan;Kim, Jongbum;Ha, PanBong;Kim, YoungHee
    • The Journal of Korea Institute of Information, Electronics, and Communication Technology
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    • v.14 no.4
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    • pp.338-347
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    • 2021
  • In this paper, the beta-ray sensor circuit used in the true random number generator was designed using DB HiTek's 0.18㎛ CMOS process. The CSA circuit proposed a circuit having a function of selecting a PMOS feedback resistor and an NMOS feedback resistor, and a function of selecting a feedback capacitor of 50fF and 100fF. And for the pulse shaper circuit, a CR-RC2 pulse shaper circuit using a non-inverting amplifier was used. Since the OPAMP circuit used in this paper uses single power instead of dual power, we proposed a circuit in which the resistor of the CR circuit and one node of the capacitor of the RC circuit are connected to VCOM instead of GND. And since the output signal of the pulse shaper does not increase monotonically, even if the output signal of the comparator circuit generates multiple consecutive pulses, the monostable multivibrator circuit is used to prevent signal distortion. In addition, the CSA input terminal, VIN, and the beta-ray sensor output terminal are placed on the top and bottom of the silicon chip to reduce capacitive coupling noise between PCB traces.

Position of Hungarian Merino among other Merinos, within-breed genetic similarity network and markers associated with daily weight gain

  • Attila, Zsolnai;Istvan, Egerszegi;Laszlo, Rozsa;David, Mezoszentgyorgyi;Istvan, Anton
    • Animal Bioscience
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    • v.36 no.1
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    • pp.10-18
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    • 2023
  • Objective: In this study, we aimed to position the Hungarian Merino among other Merinoderived sheep breeds, explore the characteristics of our sampled animals' genetic similarity network within the breed, and highlight single nucleotide polymorphisms (SNPs) associated with daily weight-gain. Methods: Hungarian Merino (n = 138) was genotyped on Ovine SNP50 Bead Chip (Illumina, San Diego, CA, USA) and positioned among 30 Merino and Merino-derived breeds (n = 555). Population characteristics were obtained via PLINK, SVS, Admixture, and Treemix software, within-breed network was analysed with python networkx 2.3 library. Daily weight gain of Hungarian Merino was standardised to 60 days and was collected from the database of the Association of Hungarian Sheep and Goat Breeders. For the identification of loci associated with daily weight gain, a multi-locus mixed-model was used. Results: Supporting the breed's written history, the closest breeds to Hungarian Merino were Estremadura and Rambouillet (pairwise FST values are 0.035 and 0.036, respectively). Among Hungarian Merino, a highly centralised connectedness has been revealed by network analysis of pairwise values of identity-by-state, where the animal in the central node had a betweenness centrality value equal to 0.936. Probing of daily weight gain against the SNP data of Hungarian Merinos revealed five associated loci. Two of them, OAR8_17854216.1 and s42441.1 on chromosome 8 and 9 (-log10P>22, false discovery rate<5.5e-20) and one locus on chromosome 20, s28948.1 (-log10P = 13.46, false discovery rate = 4.1e-11), were close to the markers reported in other breeds concerning daily weight gain, six-month weight, and post-weaning gain. Conclusion: The position of Hungarian Merino among other Merino breeds has been determined. We have described the similarity network of the individuals to be applied in breeding practices and highlighted several markers useful for elevating the daily weight gain of Hungarian Merino.

Mortality rate undergoing anesthesia in Thoroughbred racehorses at Busan Race Park (부산경남경마공원 Thoroughbred 경주마의 마취중 치사율)

  • Yang, Jaehyuk;Park, Yong-Soo
    • Journal of Practical Agriculture & Fisheries Research
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    • v.17 no.1
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    • pp.125-132
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    • 2015
  • The report about equine anesthesias in Korea are very rare. This paper aimed at the mortality rate during anesthesia in Thoroughbred horses at Equine Hospital of Busan Race Park, KRA in South Korea from 2005 to 2010. Drugs used in anesthesia was IV injection of detomidine hydrochloride (0.01 mg/kg) or xylazine(0.5mg/kg) for sedation and premedication, Guaifenesin(50-100 mg/kg) for muscle relaxation, ketamine hydrochloride(2 mg/kg) for induction of anaesthesia and Inhalational isoflurane(1.3-1.5 %) to maintain anesthesia. Total number of anesthetic cases was 190, 150 of inhalational anesthesia and 40 of general anesthesia, repectively. The purpose of anesthesia was highest in the disorder of musculoskeletal system, followed by urogenital system and respiratory system Mortality case due to anesthesia was one during arthroscopic surgery for removal of osteochondral chip fragments. The time of anesthesia was 150 min, fatal sign was hypoxemia and the reason was improper machine operation of the anesthetist. In conclusion, the perianesthetic mortality rate during anesthesia in Thoroughbred horses at Busan Race Park was 0.52%(1 death per 190 anesthetics).

A Study on the Power Converter Control of Utility Interactive Photovoltaic Generation System (계통 연계형 태양광 발전시스템의 전력변환기 제어에 관한 연구)

  • Na, Seung-Kwon;Ku, Gi-Jun;Kim, Gye-Kuk
    • Journal of the Korea Society of Computer and Information
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    • v.14 no.2
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    • pp.157-168
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    • 2009
  • In this paper, a photovoltaic system is designed with a step up chopper and single phase PWM(Pulse Width Modulation) voltage source inverter. Where proposed Synchronous signal and control signal was processed by one-chip microprocessor for stable modulation. The step up chopper operates in continuous mode by adjusting the duty ratio so that the photovoltaic system tracks the maximum power point of solar cell without any influence on the variation of insolation and temperature because solar cell has typical voltage and current dropping character. The single phase PWM voltage source the inverter using inverter consists of complex type of electric power converter to compensate for the defect, that is, solar cell cannot be developed continuously by connecting with the source of electric power for ordinary use. It can cause the effect of saving electric power. from 10 to 20[%]. The single phase PWM voltage source inverter operates in situation that its output voltage is in same phase with the utility voltage. In order to enhance the efficiency of photovoltaic cells, photovoltaic positioning system using sensor and microprocessor was design so that the fixed type of photovoltaic cells and photovoltaic positioning system were compared. In result, photovoltaic positioning system can improved 5% than fixed type of photovoltaic cells. In addition, I connected extra power to the system through operating the system voltage and inverter power in a synchronized way by extracting the system voltage so that the phase of the system and the phase of single-phase inverter of PWM voltage type can be synchronized. And, It controlled in order to provide stable pier to the load and the system through maintaining high lurer factor and low output power of harmonics.

Comparative analysis of the digital circuit designing ability of ChatGPT (ChatGPT을 활용한 디지털회로 설계 능력에 대한 비교 분석)

  • Kihun Nam
    • The Journal of the Convergence on Culture Technology
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    • v.9 no.6
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    • pp.967-971
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    • 2023
  • Recently, a variety of AI-based platform services are available, and one of them is ChatGPT that processes a large quantity of data in the natural language and generates an answer after self-learning. ChatGPT can perform various tasks including software programming in the IT sector. Particularly, it may help generate a simple program and correct errors using C Language, which is a major programming language. Accordingly, it is expected that ChatGPT is capable of effectively using Verilog HDL, which is a hardware language created in C Language. Verilog HDL synthesis, however, is to generate imperative sentences in a logical circuit form and thus it needs to be verified whether the products are executed properly. In this paper, we aim to select small-scale logical circuits for ease of experimentation and to verify the results of circuits generated by ChatGPT and human-designed circuits. As to experimental environments, Xilinx ISE 14.7 was used for module modeling, and the xc3s1000 FPGA chip was used for module embodiment. Comparative analysis was performed on the use area and processing time of FPGA to compare the performance of ChatGPT products and Verilog HDL products.