• Proceedings of the IEEK Conference
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• 2002.07b
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• pp.951-954
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• 2002

This paper presents the implementation of hash functions for IPSEC chip. There is an increasing interest in high-speed cryptographic accelerators for IPSec applications such as VPNs (virtual private networks). Because diverse algorithms are used in Internet, various hash algorithms are required for IPSec chip. Therefore, we implemented SHA-1, HAS-160 and MD5 in one chip. These hash algorithms are designed to reduce the number of gates. SHA-1 module is combined with HAS-160 module. As the result, the required logic elements are reduced by 27%. These hash algorithms have been implemented using Altera's EP20K1000EBC652-3 with PCI bus interface.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.34C no.10
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• pp.1-7
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• 1997

This paper proposes a new real-time 2-D convolver filter architecture wihtout using any multiplier. To meet the massive amount of computations for real-time image processing, several commercial 2-D convolver chips have many multipliers occupying large VLSI area. Te proposed architecture using only one shift-and-accumulator can reduce the chip size by more than 70% of commercial 2-D convolver filter chips and can meet the real-time image processing srequirement, i.e., the standard of CCIR601. In addition, the proposed chip can be used for not only 2-D image processing but also 1-D signal processing and has bood scalability for higher speed applications. We have simulated the architecture by using VHDL models and have performed logic synthesis. We used the samsung SOG cell library (KG60K) and verified completely function and timing simulations. The implemented filter chip consists of only 3,893 gates, operates at 125 MHz and can meet the real-time image processing requirement, that is, 720*480 pixels per frame and 30 frames per second (10.4 mpixels/second).

• Journal of the Korean Institute of Telematics and Electronics A
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• v.32A no.4
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• pp.57-64
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• 1995

Three models for the transformation of ferrite chip noise filter that has jagged type of electrode into cylinderical ferrite beadfilter were presented. The properties of filters were also calculated based on the proposed models. The measured properties of ferrite chip noise filter with jagged-type electrode fabricated with Ag electrode and Ni-Zn ferrite revealed that the model 3 was the best one to describe the behavior of filters. In particular, the calculated values of model 3 agreed well with measured ones as functions of electrode patterns and chip thickness. The present study showed that the properties of fiters could be designed by theoretical models and fabricated with required characteristics.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2000.05a
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• pp.621-628
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• 2000

A kinematic ball bar measuring system can analyze the various errors of a machine tool easil rapidly with only one measurement, But it cannot be used to measure the errors of the equipment the semiconductor manufacturing (e.g. chip mounter, PCB router etc.) not to use a cir interpolation. This paper presents the method to apply a kinematic ball bar measuring system tc machines which use merely a linear interpolation Also, the work of measuring and calibratir various errors of a chip mounter with a kinematic bal1 bar measurement system is accomplished

• Proceedings of the Korea Electromagnetic Engineering Society Conference
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• 2003.11a
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• pp.506-510
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• 2003

In this paper, a meander-line chip antenna with stacked layer is suggested, designed and fabricated employing the LTCC(Low Temperature Co-fired Ceramic) fabrication techniques. To reduce the antenna chip size, the meander-line antenna strip is distributed over three layer. Layers one interconnected using via holes. A 2.4 GHz chip antenna with size of $3.75{\times}7.9{\times}1.0 mm^3$ is designed and fabricated using the LTCC technique. Measurements of the fabricated antenna show 160 MHz bandwidth and 3.75 dBi maximum gain. The Measured reflection coefficient and radiation patterns agree well with the prediction by electromagnetic simulation.

• Journal of electromagnetic engineering and science
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• v.2 no.2
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• pp.93-99
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• 2002

The Cartesian loop chip which is one of key devices in narrow-band Walky-Talky transmitter using RZ-SSB modulation method was designed and implemented with 0.35 Um CMOS technology. The reduced size and low cost of transmitter were available by the use of direct-conversion and Cartesian loop chip, which improved the power efficiency and linearity of transmitting path. In addition, low power operation was possible through CMOS technology. The performance test results of transmitter showed -23 dBc improvement of IMD level and -30 dEc below suppression of SSB characteristic in the operation of Cartesian loop chip (closed-loop). At that time, the transmitting power was about 37 dBm (5 W). The main parameters to improve the transmitting characteristic and to compensate the distortion in feed back loop such as DC-offset, loop gain and phase value are interfaced with notebook PC to be controlled with S/W.

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.723-724
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• 2006

Exploiting the instruction level parallelism encountered with the limit. Single chip multiprocessor was introduced to overcome the limit of traditional processor using the instruction level parallelism. Also, a branch miss prediction is one of the causes that reduce the processor performance. In order to overcome the problems, in this paper, we make single chip multiprocessor having the idle core execute the two control flow of conditional branch. This scheme is a kind of multi-path execution technique based on single chip multiprocessor architecture.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.26 no.11
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• pp.1747-1750
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• 2022

As shrinking the semiconductor process into the deep sub-micron to achieve high-density, low power and high performance integrated circuits, MBU (multiple bit upset) by soft errors is one of the major challenge of on-chip memory systems. To address the MBU, single error correction, double error detection and double adjacent error correction (SEC-DED-DAEC) codes have been recently proposed. But these codes do not resolve mis-correction. We propose the SEC-DED-DAEC-TAED(triple adjacent error detection) code without mis-corrections. The generated H-matrix by the proposed heuristic algorithm to accomplish the proposed code is implemented as hardware and verified. The results show that there is no mis-correction in the proposed codes and the 2-stage pipelined decoder can be employed on-chip memory system.

• The Transactions of the Korean Institute of Electrical Engineers
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• v.40 no.2
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• pp.162-172
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• 1991

In proportion to the capacity enlargement of the induction motor system controlled by current source inverter, the capacitance of the commutating capacitor is enlarged and then the spike value of output voltage is increased at the moment of charge and discharge. Moreover, the output currnet includes a number of harmonic components. Such voltage spike and harmonics generate the torque ripple and lead to bad effects on the performance of the induction motor. In this study, all the harmonics excluding 17th and 19th harmonics were mostly elimunated by adopting 18-phase Triple High Frequency Current Source Inverter(HFCSI), and the spike component of output voltage was reduced by adding the Voltage Clamping Circuit(VCC). As a result, the torque ripple and the commutation loss were reduced and the performance of the system was improved. Experiments for speed control were carried out in the tripple current source inverter system for induction motor drive. Overall system was controlled by ONE CHIP MICROCOMPUTER(INTEL 8751). Control circuits were simplified and good experimental results in the constant V/F control were obtained due to the flexibility of the microcomputer.

• 제어로봇시스템학회:학술대회논문집
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• 2002.10a
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• pp.36.4-36
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• 2002

$\textbullet$ A FPGA-based One-chip position controller with the PCI interface was developed. $\textbullet$ The peripherals of the existent controller can be implemented in one FPGA device. $\textbullet$ For this purpose, the high capacity FPGA device was used. $\textbullet$ PCI controller was merged into the position controller by using the PCI controller of core form. $\textbullet$ The developed position controller used only one FPGA device to achieve the required function. $\textbullet$ By doing this, the overall system can be simplified. $\textbullet$ The noise and power dissipation problems can be minimized and it has the advantage in the price.