• 제목/요약/키워드: One-chip

검색결과 1,245건 처리시간 0.036초

Development of Pattern Classifying System for cDNA-Chip Image Data Analysis

  • Kim, Dae-Wook;Park, Chang-Hyun;Sim, Kwee-Bo
    • 제어로봇시스템학회:학술대회논문집
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    • 제어로봇시스템학회 2005년도 ICCAS
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    • pp.838-841
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    • 2005
  • DNA Chip is able to show DNA-Data that includes diseases of sample to User by using complementary characters of DNA. So this paper studied Neural Network algorithm for Image data processing of DNA-chip. DNA chip outputs image data of colors and intensities of lights when some sample DNA is putted on DNA-chip, and we can classify pattern of these image data on user pc environment through artificial neural network and some of image processing algorithms. Ultimate aim is developing of pattern classifying algorithm, simulating this algorithm and so getting information of one's diseases through applying this algorithm. Namely, this paper study artificial neural network algorithm for classifying pattern of image data that is obtained from DNA-chip. And, by using histogram, gradient edge, ANN and learning algorithm, we can analyze and classifying pattern of this DNA-chip image data. so we are able to monitor, and simulating this algorithm.

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Determination of stress state in chip formation zone by central slip-line field

  • Andrey Toropov;Ko, Sung-Lim
    • 한국정밀공학회:학술대회논문집
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    • 한국정밀공학회 2003년도 춘계학술대회 논문집
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    • pp.577-580
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    • 2003
  • Stress state of chip formation zone is one of the main problems in metal cutting mechanics. In two-dimensional case this process is usually considered as consistent shears of work material along single of several shear surfaces. separating chip from workpiece. These shear planes are assumed to be trajectories of maximum shear stress forming corresponding slip-line field. This paper suggests new approach to the constriction of slip-line field, which Implies uniform compression in chip formation zone. On the base of given model it has been found that imaginary shear line in orthogonal cutting is close to the trajectory of maximum normal stress and the problem about its determination have been considered. It has been shown that there is a second central slip-line field inside chip, which corresponds well to experimental data about stress distribution on tool rake face and tool-chip contact length. The suggested model could be useful in solution of various problems of machining.

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패턴인식 기술에 의한 칩형태 판별 (Chip type discrimination by pattern recognition technique)

  • 강종표;최만성;송지복
    • 한국정밀공학회지
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    • 제5권4호
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    • pp.32-38
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    • 1988
  • Apaptive cintrol of machine tool is aimed to change cutting state satis- factorily without aid of a machine operator, if the cuting state is abnomal such as formation of tangled ribbon type chip, built-up edge and generation of chattering and so on. Among these the recognition of chip type is one of the most important since it has imlications relate to : 1. Safety of operator 2. Stoppage of work due to entanglment in tool and workpiece of chip 3. Problem of producted chip control In this paper the chip type is discriminatied by the pattern recognition technique. It is found that the power spectrum of cutting force for each chip type has it's own special pattern. Linear discriminant function for the recognition of the chip type is obtained by learning process. The discriminant function can be the basis of adaptive control for the rate of success of recognition by pattern recognition technique is at leasthigher than 83%.

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해석적 최적 칩파형의 BER과 전송성능(Throughput) 분석 (BER and Throughput Analyses of the Analytical Optimum Chip Waveform)

  • Ryu, Heung-Gyoon;Chung, Ki-Ho;Lee, Dong-Hun
    • 한국전자파학회논문지
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    • 제13권7호
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    • pp.641-648
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    • 2002
  • The study on the chip waveform design to minimize multiple-access interference (MAI) and its performance evaluation are very important since chip waveform decides the signal quality and system capacity of the direct-sequence CDMA wireless communication system. This paper suggests the analytical chip waveform to minimize the MAI. The BER and throughput performances achieved by the proposed analytical optimum chip waveform are compared with those of the conventional chip waveforms in the Nakagami-m distribution frequency selective channel when the differential phase shift keying (DPSK) is employed in DS-CDMA system. From the numerical results, capacity and throughput are improved about 2 times and 1.4 times respectively when it is compared with the Kaiser chip waveform that is considered as one of the best in the conventional ones.

선삭가공시 절삭조건에 의한 Chip형태의 분류와 예측에 관한 연구 (A Study on the Classification and Prediction of the Chip Type under the Specified Cutting Conditions in Turning)

  • Sim, G.J.;Cheong, C.Y.;Seo, N.S.
    • 한국정밀공학회지
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    • 제12권8호
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    • pp.53-62
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    • 1995
  • In recent years, the rapid development of the machine tool and tough insert has made metal removal rates increase, and automatic system without human supervision requires a higher degree reliability of machining process. Therefore the control of chips is one of the important topics which deserves much attention. The chip classification was made based upon standard deviation of the mean cutting force measured by a tool dynamometer. STS304was chosen as the workpiece which is known as the difficult-to-cut material and mainly saw-toothed chip produced, and the chip type according to the standard deviation of mean cutting force was classified into five categories in this experiment. Long continuous type chip which interrupts the normal cutting process, and damages the operator, tool and workpiece has low standard deviation value, while short broken type chip, which is favourable chip for disposal, has relatively large standard deviation value. In addition, we investigated the possibility that the chip type can be predicted analyzing the relationship between chip type and cutting condition by the trained neural network, and obtained favourable results by which the chip type can be predicted with cutting conditon before cutting process.

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선삭가공의 칩형상 해석 (I) -칩흐름각 해석- (Analysis of the Chip Shape in Turing (I) -Analysis of the Chip Flow Angle-)

  • 이영문;최수준;우덕진
    • 대한기계학회논문집
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    • 제15권1호
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    • pp.139-144
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    • 1991
  • 본 연구에서는 절삭가공시 생성되는 칩의 형상해석의 일환으로 2차원 절삭시 칩은 절삭날에 수직한 방향으로 공구경사면을 흘러간다는 기본적인 전제조건과 Kluft 등의 칩흐름각 예측에 대한 제안중 노으즈반경(nose radius) 및 기울임각의 영향을 중 첩시키고, 또한 절삭날에 연하여 미변형 칩두께(undeformed chip thickness)가 달라지 는 경우 칩흐름의 세기는 이에 비례한다는 Baart등의 가정을 도입하여 칩흐름각에 대 한 새로운 해석을 시도하였다.

신경회로망과 실험계획법을 이용한 칩형상 예측 (Prediction of Chip Forms using Neural Network and Experimental Design Method)

  • 한성종;최진필;이상조
    • 한국정밀공학회지
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    • 제20권11호
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    • pp.64-70
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    • 2003
  • This paper suggests a systematic methodology to predict chip forms using the experimental design technique and the neural network. Significant factors determined with ANOVA analysis are used as input variables of the neural network back-propagation algorithm. It has been shown that cutting conditions and cutting tool shapes have distinct effects on the chip forms, so chip breaking. Cutting tools are represented using the Z-map method, which differs from existing methods using some chip breaker parameters. After training the neural network with selected input variables, chip forms are predicted and compared with original chip forms obtained from experiments under same input conditions, showing that chip forms are same at all conditions. To verify the suggested model, one tool not used in training the model is chosen and input to the model. Under various cutting conditions, predicted chip forms agree well with those obtained from cutting experiments. The suggested method could reduce the cost and time significantly in designing cutting tools as well as replacing the“trial-and-error”design method.

플립칩의 매개변수 변화에 따른 보드레벨의 동적신뢰성평가 (Dynamic Reliability of Board Level by Changing the Design Parameters of Flip Chips)

  • 김성걸;임은모
    • 한국생산제조학회지
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    • 제20권5호
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    • pp.559-563
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    • 2011
  • Drop impact reliability assessment of solder joints on the flip chip is one of the critical issues for micro system packaging. Our previous researches have been showing that new solder ball compositions of Sn-3.0Ag-0.5Cu has better mechanical reliability than Sn-1.0Ag-0.5Cu. In this paper, dynamic reliability analysis using Finite Element Analysis (FEA) is carried out to assess the factors affecting flip chip in drop simulation. The design parameters are size and thickness of chip, and size, pitch and array of solder ball with composition of Sn1.0Ag0.5Cu. The board systems by JEDEC standard including 15 chips, solder balls and PCB are modeled with various design parameter combinations, and through these simulations, maximum yield stress and strain at each chip are shown at the solder balls. It is found that larger chip size, smaller chip array, smaller ball diameter, larger pitch, and larger chip thickness have bad effect on maximum yield stress and strain at solder ball of each chip.

엔드밀링 절삭력에 미치는 공구형상오차 I- 상향 엔드밀링 - (Effects of Cutter Runout on End Milling Forces I-Up Eng Milling-)

  • 이영문;양승한;송태성;권오진;백승기
    • 한국정밀공학회지
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    • 제19권8호
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    • pp.63-70
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    • 2002
  • In end milling process, the undeformed chip section area and cutting forces vary periodically with phase change of the tool. However the real undeformed chip section area deviates from the geometrically ideal one owing to cutter runout and tool shape error. In this study, a method of estimating the real undeformed chip section area which reflects cutter runout and tool shape error was presented in up end milling process using measured cutting forces. The average specific cutting resistance, Ka is defined as the main cutting force component divided by the modified chip section area. Ka value becomes smaller as the helix angle increases from $30^circC \;to\;40\circC$. But it becomes larger as the helix angle increases from $40^\circ$to 50 . On one hand, the Ka value shows a tendency to decrease with increase of the modified chip section area and this tendency becomes distinct with smaller helix angle.

원칩 마이크로 컴퓨터를 이용한 UPS용 3상 다중 PAM 인버터에 관한 연구 (A Study on the Three Phase Multi-PAM Inverter using the one-chip Microcomputer for UPS.)

  • 김성백;이종규
    • 한국조명전기설비학회지:조명전기설비
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    • 제3권2호
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    • pp.63-68
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    • 1989
  • 정지형 전원(Static Power Supply) 설계를 위한 다중 PAM 인버터에 관하여 논한다. 인버터의 제어부는 원칩 마이크로 컴퓨터(One-chip Microcomputer)로 구성하여 간단히 제어신호를 얻었고, 종단 구성은 더블 브리지 인버터와 3상 3권선 변압기로 구성하였다. 출력 파형은 제어기와 변압기를 이용하여 1주기당 22 스텝의 전압레벨로 다중 PAM파형을 합성하였으며, 저역 여파기(Low Pass Filter)에 의해 정현파에 가까운 파형을 얻었다.

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