• International Journal of Precision Engineering and Manufacturing
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• v.4 no.1
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• pp.9-14
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• 2003

In this study we suggest real-time simulator that could describe rent system without ordinary DSP card. This simulator is composed of 80196kc-16bit ordinary microprocessor, which is widely used up to now and personal computer. DSP card that has calculated complex numerical equation is replaced by personal computer and 80196kc generates control signals independently out of the personal computer. In all process personal computer is synchronized with one-board microprocessor (80196kc) within sampling time in the closed loop system. This makes it possible to be described in hydraulic servo system in real time.

• 제어로봇시스템학회:학술대회논문집
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• 2000.10a
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• pp.191-191
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• 2000

Hydraulic servo system is difficult to be made up and each component is very expensive, it takes long for actual system to make and test and it costs a high price. Because of these characteristics of hydraulic servo system, a real time simulator that could describe behavior of real system is highly demanded, without composing real hydraulic system. So, many studies have been (lone on these subjects and many simulators are developed with superiority. Since the nonlinearity of a hydraulic system common simulator have composed of many calculative times byusing DSP(Digital Signal processing) and have made it possible to find the situations of the system in real time, calculating hydraulic simulation and controller separately. In this study, we suggest real-time simulator that could describe real system without ordinary DSP card. This simulator is composed of 80196kc and personal computer. DSP card that has calculated complex numerical equation is supplanted by personal computer and 80196kc generates control signals independently out of the personal computer. In all process, personal computer is synchronized with one-board microprocessor within sampling time in the closed loop system. This makes it possible to be described in hydraulic servo system in real time. And to make a comparison between the result of the real-time simulator and a hydraulic servo system.

• 제어로봇시스템학회:학술대회논문집
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• 1986.10a
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• pp.225-231
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• 1986

A design of an industrial microcomputer control system for an one-through tube boiler using oil is presented. The microcomputer system is based on standard iSBC 88/40 board. The software consist of a RTE(real time executive) and application tasks. The designed control system saves fuel and gives a more reliable over-all operation.

• Journal of Institute of Control, Robotics and Systems
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• v.5 no.6
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• pp.691-697
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• 1999

This paper describes the implementation of a high speed image processing board. This image processing board is consist of a image acquisition part and a image processing part. The image acquistion part is digitizing the image input data from CIS and save it to the dual port RAM. By putting on the dual port memory between two parts, during acquistion of image, the image processing part can be effectively processing of large-volume image data. Most of all image preprocessing part are integrated in a large-scaled FPGA. We arwe using ADSP-2181 of the Analog Device Inc., LTD. for a image processing part, and using the available all memory of DSP for the large-volume image data. Especially, using of IDMA exchanges the data with the external microprocessor or the external PC, and can watch the result of image processing and acquired image. Finally, we show that an implemented image processing board used for the simulation of image retreval by the one of the typical application.

• Journal of the Korean Institute of Telematics and Electronics
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• v.21 no.5
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• pp.79-89
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• 1984

In this paper we present development of microprocessor-based 8-channel statistical multiplexer (SMUX). The hardware design includes one Z-80A CPU board with the clock rate of 4 MHz, one 16 Kbyte ROM board for program storage, one 16 Kbyte dynamic RAM board and three I/O boards, all connected through an S-100 compatible tristate bus. The SMUX can presently multiplex 8 channels with data rates ranging 50 bps to 9600 bps, but can be reduced to accommodate 4 channels by having a slight modification of software and removing one terminal I/O board. The system specifications meet CCITT recommendations X.25 link level, V.24, V.28, X.3 and X.28. Significant features of the SMUX are its capability of handling 4 input codes (ASCII, EBCDIC, Baudot, Transcode), the use of a dynamic buffer management algorithm, a diagnostic facility, and the efficient use of a single CPU for all system operation. Throughout the paper, detailed explanations are given as to how the hardware and software of the SMUX system have been designed efficiently.

• Proceedings of the Korean Institute of Intelligent Systems Conference
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• 1993.06a
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• pp.975-976
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• 1993

This talk presents the overview of the author's research and development activities on fuzzy inference hardware. We involved it with two distinct approaches. The first approach is to use application specific integrated circuits (ASIC) technology. The fuzzy inference method is directly implemented in silicon. The second approach, which is in its preliminary stage, is to use more conventional microprocessor architecture. Here, we use a quantitative technique used by designer of reduced instruction set computer (RISC) to modify an architecture of a microprocessor. In the ASIC approach, we implemented the most widely used fuzzy inference mechanism directly on silicon. The mechanism is beaded on a max-min compositional rule of inference, and Mandami's method of fuzzy implication. The two VLSI fuzzy inference chips are designed, fabricated, and fully tested. Both used a full-custom CMOS technology. The second and more claborate chip was designed at the University of North Carolina(U C) in cooperation with MCNC. Both VLSI chips had muliple datapaths for rule digital fuzzy inference chips had multiple datapaths for rule evaluation, and they executed multiple fuzzy if-then rules in parallel. The AT & T chip is the first digital fuzzy inference chip in the world. It ran with a 20 MHz clock cycle and achieved an approximately 80.000 Fuzzy Logical inferences Per Second (FLIPS). It stored and executed 16 fuzzy if-then rules. Since it was designed as a proof of concept prototype chip, it had minimal amount of peripheral logic for system integration. UNC/MCNC chip consists of 688,131 transistors of which 476,160 are used for RAM memory. It ran with a 10 MHz clock cycle. The chip has a 3-staged pipeline and initiates a computation of new inference every 64 cycle. This chip achieved an approximately 160,000 FLIPS. The new architecture have the following important improvements from the AT & T chip: Programmable rule set memory (RAM). On-chip fuzzification operation by a table lookup method. On-chip defuzzification operation by a centroid method. Reconfigurable architecture for processing two rule formats. RAM/datapath redundancy for higher yield It can store and execute 51 if-then rule of the following format: IF A and B and C and D Then Do E, and Then Do F. With this format, the chip takes four inputs and produces two outputs. By software reconfiguration, it can store and execute 102 if-then rules of the following simpler format using the same datapath: IF A and B Then Do E. With this format the chip takes two inputs and produces one outputs. We have built two VME-bus board systems based on this chip for Oak Ridge National Laboratory (ORNL). The board is now installed in a robot at ORNL. Researchers uses this board for experiment in autonomous robot navigation. The Fuzzy Logic system board places the Fuzzy chip into a VMEbus environment. High level C language functions hide the operational details of the board from the applications programme . The programmer treats rule memories and fuzzification function memories as local structures passed as parameters to the C functions. ASIC fuzzy inference hardware is extremely fast, but they are limited in generality. Many aspects of the design are limited or fixed. We have proposed to designing a are limited or fixed. We have proposed to designing a fuzzy information processor as an application specific processor using a quantitative approach. The quantitative approach was developed by RISC designers. In effect, we are interested in evaluating the effectiveness of a specialized RISC processor for fuzzy information processing. As the first step, we measured the possible speed-up of a fuzzy inference program based on if-then rules by an introduction of specialized instructions, i.e., min and max instructions. The minimum and maximum operations are heavily used in fuzzy logic applications as fuzzy intersection and union. We performed measurements using a MIPS R3000 as a base micropro essor. The initial result is encouraging. We can achieve as high as a 2.5 increase in inference speed if the R3000 had min and max instructions. Also, they are useful for speeding up other fuzzy operations such as bounded product and bounded sum. The embedded processor's main task is to control some device or process. It usually runs a single or a embedded processer to create an embedded processor for fuzzy control is very effective. Table I shows the measured speed of the inference by a MIPS R3000 microprocessor, a fictitious MIPS R3000 microprocessor with min and max instructions, and a UNC/MCNC ASIC fuzzy inference chip. The software that used on microprocessors is a simulator of the ASIC chip. The first row is the computation time in seconds of 6000 inferences using 51 rules where each fuzzy set is represented by an array of 64 elements. The second row is the time required to perform a single inference. The last row is the fuzzy logical inferences per second (FLIPS) measured for ach device. There is a large gap in run time between the ASIC and software approaches even if we resort to a specialized fuzzy microprocessor. As for design time and cost, these two approaches represent two extremes. An ASIC approach is extremely expensive. It is, therefore, an important research topic to design a specialized computing architecture for fuzzy applications that falls between these two extremes both in run time and design time/cost. TABLEI INFERENCE TIME BY 51 RULES {{{{Time }}{{MIPS R3000 }}{{ASIC }}{{Regular }}{{With min/mix }}{{6000 inference 1 inference FLIPS }}{{125s 20.8ms 48 }}{{49s 8.2ms 122 }}{{0.0038s 6.4㎲ 156,250 }} }}

• Journal of Biosystems Engineering
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• v.15 no.2
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• pp.110-122
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• 1990

This study was undertaken to develop the feed rate control system for the head feed thresher by making use of the microprocessor and to evaluate the response of the system to a various threshing conditions. The control unit was composed of one-board microcomputer. The speed of the wet-paddy feeding chain was controlled by dc moter with PI controller. It was used the adaptive control method to maintain the constant feed rate regardless of the fed rice varieties. The sliding type potentiometer was used as the feed rate sensor, which was attached on the sheaf-holding apparatus. The mathematical models of the system components were derived and computer simulation was developed for investigating the parameters affecting on control performance and for estimating the response of the system. A one-board microcomputer-based feed rate control system developed in this study was properly functioned and assessed as adequate for the feed rate control system of the head feed thresher. Based on the simulation for the bundle feed, it was anticipated that the lower setting value of the cylinder speed(RL) is to be set higher than the limiting operational speed. In addition, the higher setting value of the cylinder speed(RH) is to be set lower than the limiting cylinder speed for threshing. The computer simulation for the continuous spread feed showed that the lower the setting value of straw layer thickness(LL) was set, the shorter the correction time. However, if too low LL may be established, the feed rate could not reach to its desired rate.

• Journal of Biosystems Engineering
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• v.25 no.5
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• pp.351-358
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• 2000

This study was conducted to develop a speed control system of a DC motor which drove a barley seeder mounted on a combine harvester. Barley seeder mounted on a combine has been known to reduce labor and cost of barley cultivation. However, development of the seeder has been unsuccessful because the combine, a dedicated rice and barley harvester has not enough space and proper power take-off for barley seeder. To develop a barley seeder, small powered motor speed controller was required. A proximity sensor for detecting working speed of the combine and a programmable one board microprocessor was used to develope a control system. Motor parameters and motor constant, relationship between seeding rate, motor speed, groove volumes of a tested roller, torque were measured. The proximity sensor sent a frequency signal to the microprocessor. In laboratory experiments, the excitation voltage of the motor was shown not to be proportional to the size of pulse width (duty ratio). A table transforming frequency signal, that represented for working speed to proper pulse width was developed from seeding rate experiments. However, seeding rate at low frequency signal was not proportional to the working speed. Seeding rate control proportional to the frequency signal was achieved by shifting of the frequency signal.

• Proceedings of the KIEE Conference
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• 1997.07b
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• pp.724-727
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• 1997

This paper describes a control method of tank level using Fuzzy Inference Technique. In General, to control tank level without a dangerous overflow and with a high accuracy is difficult because of high order time delay and nonlinearity. None the less, the hardware controller using 80586 Microprocessor with DT-2801 board in this paper was successfully implemented, through a series of simulations and experiments, the superiority of the proposed fuzzy controller ta a conventional PID one was investigated.

• Journal of the Korean Society for Precision Engineering
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• v.21 no.10
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• pp.94-101
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• 2004

This paper presents the development of a keypad test system for the improvement of working environment and productivity using PTC 16F877 microprocessor. In order to detect the fault of keypad products, hardware and software design is performed in this system. Keypad fault detection system is controlled by the 8 bit one chip PIC microcontroller for the exactness and speed. Developed panel of the keypad test system is comprised of the sub-panel for selecting in the inspected keypad types and the main panel f3r displaying the working order and fault position. Furthermore, all data from keypad inspection are stored in main memory of personal computer for the database. All these functions lead to the improvement of working speed and environment.