• Journal of information and communication convergence engineering
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• 제10권1호
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• pp.85-90
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• 2012

A 40-MS/sec 10-bit pipelined analog to digital converter (ADC) with a 1.2 Vpp differential input signal is proposed. The implemented pipelined ADC consists of eight stages of 1.5 bit/stage, one stage of 2 bit/stage, a digital error correction block, band-gap reference circuit & reference driver, and clock generator. The 1.5 bit/stage consists of a sub-ADC, digital to analog (DAC), and gain stage, and the 2.0 bit/stage consists of only a 2-bit sub-ADC. A bootstrapped switch with a constant resistance is proposed to improve the linearity of the input switch. It reduces the maximum VGS variation of the conventional bootstrapped switch by 67%. The proposed bootstrapped switch is used in the first 1.5 bit/stage instead of a sample-hold amplifier (SHA). This results in the reduction of the hardware and power consumption. It also increases the input bandwidth and dynamic performance. A reference voltage for the ADC is driven by using an on-chip reference driver without an external reference. A digital error correction with a redundancy is also used to compensate for analog noise such as an input offset voltage of a comparator and a gain error of a gain stage. The proposed pipelined ADC is implemented by using a 0.18-${\mu}m$ 1- poly 5-metal CMOS process with a 1.8 V supply. The total area including a power decoupling capacitor and the power consumption are 0.95 $mm^2$ and 51.5 mW, respectively. The signal-to-noise and distortion ratio (SNDR) is 56.15 dB at the Nyquist frequency, resulting in an effective number of bits (ENOB) of 9.03 bits.

• 대한인간공학회지
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• 제34권1호
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• pp.75-83
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• 2015

Objective: The aim of this study is to suggest the standard of the direction sign on the pendant switch of overhead cranes which can reduce human errors in control. Background: A great number of crane accidents occur in industries. One of the major causes of the accidents is the mistake in the control of cranes by confusing the orientation of crane movements. Nevertheless, three different direction sign styles, 'East, West, South, North (EWSN)', 'Forward, Backward, Left, Right (FBLR)', and arrows for four directions are used without standardization. Method: An overhead crane simulator was installed for a laboratory experiment. It could move along six directions by the control of a pendant switch. 90 participants were evenly assigned to the three different conditions of direction sign styles. The participants were asked to control the pendant switch according to the continuously appearing 16 direction signs on a monitor ahead. The participants were allowed to refer an orientation sign board on the ceiling representing correct movement directions of the overhead crane simulator. Results: The direction sign style, 'EWSN', showed statistically significant better performance in task completion time and number of errors than the other sign styles. The direction sign style, 'EWSN', adopting the cardinal direction system, made the participants clear in direction controls after customizing to the crane movements. However, the direction sign styles, 'FBLR' and the arrows adopting the relative direction system made conflicts in direction controls due to the egocentric view of human. Conclusion: The direction sign style, 'EWSN', is the most appropriate for the standardization of the direction sign on the pendant switch of overhead cranes. Application: The results of this study can be applied to the standardization of direction sign in the legal notification on the safety certifications of crane manufacturing.

• 한국전자통신학회논문지
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• 제10권2호
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• pp.211-218
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• 2015

본 논문에서는 클라우드 컴퓨팅 서비스를 위한 가상 네트워크 구축에 필요한 중요 구성 요소 중의 하나인 가상스위치를 Intel DPDK(Data Plane Development Kit)를 이용하여 구현하고 DPDK에서 지원하는 가속화 가상스위치의 기능을 테스트 및 검증하였다. 최근 사물인터넷 등에서와 같이 지능형 IT 시스템들의 인터넷 접속을 통한 새로운 정보 서비스 플랫폼의 출현과 그에 대한 활용 및 응용 서비스를 기업 비즈니스에 적용하고자 하는 기업이 많아지고 있다. 기업들은 매우 빠른 소비자 환경변화에 민첩하게 대응할 수 있는 신규 서비스에 대한 사용자 입장에서의 클라우드 컴퓨팅 활용 측면으로 적은 비용으로 신규 서비스를 빠른 시일 내에 적용할 수 있다. 본 연구에서는 창조적 서비스 사업에 활용할 수 있는 스마트 클라우드 플랫폼 서비스를 효율적으로 구현하기 위한 고속 가상스위치를 Intel DPDK를 이용하여 구현하고 그의 기능 검증에 대한 연구를 수행하였다.

• Journal of Electrical Engineering and Technology
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• 제8권5호
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• pp.1107-1115
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• 2013

A new PWM technique for a two-phase BLDC motor fed by a two-phase eight-switch inverter is proposed in this paper. It is well known that a two-phase eight-switch inverter can significantly improve power output compared with a two-phase six-switch inverter in a two-phase motor drive. To drive the two-phase BLDC motor simply and effectively, two normal PWM strategies are investigated to manage speed regulation. However, under the conditions of low speed and light load, especially during the braking process, the current in a short time of one period is near zero, which is a discontinuous waveform every half period. To solve it, a novel PWM technique is investigated to improve the operational performance of normal technique. Using the new PWM scheme, the current continues every half period and the braking performance is improved. The effectiveness of the proposed PWM method is verified through the experiments.

• Journal of Electrical Engineering and Technology
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• 제9권6호
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• pp.1822-1831
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• 2014

Micro-grid is connected to the main power grid through a static switch. One of the critical issues in micro-grids is protection which must disconnect the micro-grid from the network in short-circuit contingencies. Protective methods of micro-grid mainly follow the model of distribution system protection. This protection scheme suffers from improper operation due to the presence of single-phase loads, imbalance of three-phase loads and occurrence of power swings in micro-grid. In this paper, a new method which prevents from improper performance of static micro-grid protection is proposed. This method works based on artificial neural network (ANN) and able to differentiate short circuit from power swings by measuring impedance and the rate of impedance variations in PCC bus. This new technique provides a protective system with higher reliability.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2004년도 전력전자학술대회 논문집(1)
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• pp.321-324
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• 2004

This paper presents a package IC containing some components of DC/DC converter block for mobile phone's sub OLED(Organic Light Emitting Display). Package IC contains a load switch, a control IC, a diode, a switch for on/off operation, and a switch for changing output voltage. It operates with switching frequency of 100kHz, within the range of input voltage, $3.2V\~5.5V$. Duty ratio can be changed up to $93\%$, and maximum power efficiency is $85\%$. This package IC is loaded onto three model of 1.2W mobile phone's sub-OLED.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2008년도 하계학술대회 논문집
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• pp.505-507
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• 2008

A conventional active-clamp forward (ACF) converter is a favorable candidate in low-to-medium power applications. However, the switches suffer from high voltage stress, i.e., sum of the input voltage and the reset capacitor voltage. Therefore, it is not suitable for high input voltage applications such as a front-end converter of which the input voltage is about 400-$V_{dc}$. To solve this problem, three-switch ACF (TS-ACF) converter, which employs two main switches and one auxiliary switch with low voltage stress, is proposed. Utilizing low-voltage rated switches, the proposed converter is promising for high input voltage applications with high efficiency and low cost.

• 전력전자학회논문지
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• 제18권2호
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• pp.199-204
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• 2013

Recently, the demand for fuel efficient electric vehicles (EVs) and hybrid electric vehicles (HEVs) has been growing globally. Due to the increased number of switching devices in the electrified vehicles, the probability of the semiconductor device failure is much higher than in other application areas. A sudden failure in one of the power switches and insufficient power management ability in the systems not only decreases system performance, but also leads to critical safety problems. In this paper, novel switch open circuit fault detection method is proposed, and the proposed approach is verified by experiments.

• 한국통신학회논문지
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• 제21권11호
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• pp.2850-2861
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• 1996

This paper describes the design of AATM switch LIS of shared buffer type with linked-list architecture to control memory access. The proposed switch LSI consists of the buffer memory, controller and FIFO memory blocks and two special circuits to avoid the cell blocking. One of the special circuit is a new address control scheme with linked-list architecture which maintains the address of buffer memory serially ordered from write address to read address. All of the address is linked as chain is operated like a FIFO. The other is slip-flag register it will be hold the address chain when readaddress missed the reading of data. The circuits control the buffer memory efficiently and reduce the cell loss rate. As a result the designed chip operates at 33ns and occupied on 2.7*2.8mm$^{2}$ using 0.8.mu.m CMOS technology.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2001년도 하계종합학술대회 논문집(1)
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• pp.383-386
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• 2001

This paper presents a novel multicast architecture for shared multibuffer ATM switch, which is tailored for throughput enhancement in multicast environments. The address queues for multicast cells are separated from those for unicast cells to arbitrate multicast cells independently from unicast cells. Three read cycles are carried out during each cell slot and multicast cells have chances to be read from shared buffer memory(SBM) in the third read cycle provided that the shared memory is not accessed to read a unicast cell. In this architecture, maximum two cells are queued at each fabric output port per time slot and output mask choose only one cell. Extensive simulations are carried out and it shows that the proposed architecture has enhanced throughput comparing with other multicast schemes in shared multibuffer switch architecture.