• Journal of the Korean Magnetics Society
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• v.13 no.3
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• pp.109-114
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• 2003

The purpose of this study Is to investigate the effect of $V_2$O$_{5}$ addition on the microstructures and magnetic properties of 7.7${\times}$4.5${\times}$1.0 mm sized multi-layer chip inductors prepared by the screen printing method using 0∼0.5 wt％ $V_2O_{5}$-doped NiCuZn ferrite pastes. With increasing the $V_2O_{5}$ content, the exaggerated grain growth of ferrite layers was developed due to the promotion of Ag diffusion and Cu segregation into the grain boundaries oi ferrites, which affected significantly the magnetic properties of the chip inductors. After sintering at $900^{\circ}C$, the inductance at 10 MHZ of the 0.5 wt％ $V_2O_{5}$-doped chip inductor was 3.7 ${\mu}$H less than 4.2 ${\mu}$H of the 0.3 wt% $V_2O_{5}$-doped one, which was thought to be caused by the residual stress at the ferrite layers increased with the promotion of Ag diffusion and Cu segregation. The quality factor of the 0.5 wt% $V_2O_{5}$-doped chip inductor decreased with increasing the sintering temperature, which was considered to be caused by the electrical resistivity of the ferrite layer decreased with the promotion of Ag/cu segregation at the grain boundaries and the growth of the mean grain size of ferrite due to exaggerated grain growth of ferrite layers.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.56 no.11
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• pp.1967-1971
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• 2007

In this paper, we verified basic forms and equivalent circuits of spiral inductors and various kinds of parasitics of equivalent circuits by using HFSS and Nexxim program that were 3-D EM analysis tools, and fabrication on-chip spiral inductors using Hynix's 0.25um 1-poly and 5-metal CMOS process. Comparing with PGS(patterned ground shield) and NPGS(non patterned ground shield) of spiral inductors of 3.5 turn, 4.5 turn and 5.5 turn, etc, the application of PGS could improve maximum Q value by 8-12%.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.6
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• pp.34-42
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• 2000

Recently, there is a growing need to develope small-size RF chip inductors operating to GHz to realize high-performance, micro-fabricated wireless communication products. For the development of high-performance RF chip inductors, however, the ferrite-based chip inductors can not be used above 300MHz due to the limitation of the permeability of this material. In this work, small-size, high-performance RF chip inductors utilizing amorphous $Al_2O_3$ core material were investigated. Copper (Cu) with 40${\mu}m$ diameter was used as the coils and the chip inductor size fabricated in this work is $2.1mm{\times}1.5mm{\times}1.0mm$. The external current source was applied after bonding Cu coil leads to gold pads electro-plated on the bottom edges of a core material. The composition of core materials was measured using a EDX. High frequency characteristics of the inductance (L), quality factor (Q), and impedance (Z) of developed inductors were measured using an RF Impedance/Material Analyzer (HP4291B with HP16193A test fixture). The developed inductors have the self-resonant frequency (SRF) of 1 to 3.5 GHz and exhibit L of 22 to 150 nH. The L of the inductors decreases with increasing the SRF. The Z of the inductors has the maximum value at the SRF and the inductors have the quality factor of 70 to 97 in the frequency range of 500 MHz to 1.5 GHz.

• KIEE International Transactions on Electrophysics and Applications
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• v.5C no.4
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• pp.176-179
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• 2005

The increasing demand for high density packaging technologies and the evolution to mixed digital and analogue devices has been the con-set of increasing research in thin film multi-layer technologies such as the passive components integration technology. In this paper, Cu and TaO thin film with RF sputtering was deposited for spiral inductor and MOM capacitor on the $SiO_2$/Si(100) substrate. MOM capacitor and spiral inductor were fabricated for L-C band pass filter by sputtering and lift-off. We are analyzed and designed thin films L-C passive components for band pass filter at 900 MHz and 1.8 GHz, important devices for mobile communication system. Based on the high-Q values of passive components, MOM capacitor and spiral inductors for L-C band pass filter, a low insertion loss of L-C passive components can be realized with a minimized chip area. The insertion loss was 3 dB for a 1.8 GHz filter, and 5 dB for a 900 MHz filter. This paper also discusses a analysis and practical design to thin-film L-C band pass filter.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.22 no.10
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• pp.826-831
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• 2009

In this paper, a high power RF amplifier module using AlN substrate of high thermal conductivity has been proposed. This RF amplifier module has the advantage of compact size and effective heat dissipation for the packaging of high power chip. To fabricate the thru-hole and scribing line on AlN substrate, the key parameters of $CO_2$ laser were experimented. And then, microstrip lines and spiral planar inductors were fabricated on an AlN substrate using the thin-film process. The fabricated microstrip lines on the AlN substrate has an attenuation value of 0.1 dB/mm up to 10 GHz. The fabricated spiral planar inductor has a high quality factor, a maximum of about 62 at 1 GHz for a 5.65 nH inductor. Packaging of a RF power amplifier was implemented on an AlN substrate with thru-hole. From the measured results, the gain is 24 dB from 13 to 15 GHz and the output power is 33.65 dBm(2.3 W).

• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.2
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• pp.301-306
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• 2015

An ultra-compact and wideband low noise amplifier (LNA) in a quad flat non-leaded (QFN) package is presented. The LNA monolithic microwave integrated circuit (MMIC) is implemented in a $0.25{\mu}m$ GaN IC technology on a Silicon Carbide (SiC) substrate provided by Triquint. A source degeneration inductor and a gate inductor are used to obtain the noise and input matching simultaneously. The resistive feedback and inductor peaking techniques are employed to achieve a wideband characteristic. The LNA chip is mounted in the $3{\times}3-mm^2$ QFN package and measured. The supply voltages for the first and second stages are 14 V and 7 V, respectively, and the total current is 70 mA. The highest gain is 13.5 dB around the mid-band, and -3 dB frequencies are observed at 0.7 and 12 GHz. Input and output return losses ($S_{11}$ and $S_{22}$) of less than -10 dB measure from 1 to 12 GHz; there is an absolute bandwidth of 11 GHz and a fractional bandwidth of 169%. Across the bandwidth, the noise figures (NFs) are between 3 and 5 dB, while the output-referred third-order intercept points (OIP3s) are between 26 and 28 dBm. The overall chip size with all bonding pads is $1.1{\times}0.9mm^2$. To the best of our knowledge, this LNA shows the best figure-of-merit (FoM) compared with other published GaN LNAs with the same gate length.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.6
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• pp.16-24
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• 2009

In this paper, DC-DC buck converter with on-chip filter inductor and capacitor is presented. By operating at high switching frequency of 50MHz with stacked interleaved topology, we reduced inductor and capacitor sizes compared to previously published DC-DC buck converters. The proposed circuit is designed in a standard $0.5{\mu}m$ CMOS process, and chip area is $9mm^2$. This circuit operated at the input voltage of $3{\sim}5V$ range, the maximum load current of 250mA, and the maximum efficiency of 71%.

• ETRI Journal
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• v.35 no.3
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• pp.554-557
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• 2013

This letter presents a power amplifier (PA) with an on-chip power detector for 2.4-GHz wireless local area network application. The power detector consists of a clamp circuit, a diode detector, and a coupled line directional coupler. A series inductor for an output matching network in the PA is combined with a through line of the coupler, which reduces the coupling level. Therefore, the coupler employs a metamaterial-based transformer configuration to increase coupling. The amount of coupling is increased by 2.5 dB in the 1:1 symmetric transformer structure and by 4.5 dB from two metamaterial units along the coupled line.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.18 no.5 s.120
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• pp.539-546
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• 2007

In this paper, a 3-D EM simulation methodology for on-chip spiral inductor analysis has provided and it is shown that the methodology can be adapted to the highly predictable design for CMOS VCO. LC-resonator type VCO have fabricated by using standard 0.25 um CMOS process. And the LC VCO layout case which has pattern ground shielded inductors and the other layout case which has no pattern grounded inductors were fabricated for the verification of their effects on the VCO's phase noise by reducing the Q-factor of inductors. Fabricated VCO has 3.094 GHz, -12.15 dBm output at the tuning voltage of 2.5 V, and from the simulation, Q-factor of the pattern grounded inductor has increased 8% at 3 GHz, and from the measurement results, the phase noise has reduced by 9 dB at the 3 MHz off-set frequency for the pattern grounded inductor layout case.

• Proceedings of the IEEK Conference
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• 2005.11a
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• pp.909-912
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• 2005

According to miniaturization trend of rehabilitation medical equipment such as hearing aid, study to replace previous complex system with semiconductor SOC (System-on-Chip) chip becomes lively. In this study, after investigating of existent hearing aid performance in circuit design approach, low electric power consuming, single power supply (1.4V battery) CMOSS OP AMP was designed. Analog circuit design tools such as Hspice and Cadence were used for circuit simulation and implementing layout design. This study shows technical methods particularly for layout design. The work is done in pmos and nmos active element layout design in addition to passive element design such as resister, capacitor and inductor.