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Stacked Interleaved Buck DC-DC Converter With 50MHz Switching Frequency  

Kim, Young-Jae (Dep. of Electronic, Electrical, Control and Instrumentation Engineering, Hanyang Univ.)
Nam, Hyun-Seok (Dep. of Electronic, Electrical, Control and Instrumentation Engineering, Hanyang Univ.)
Ahn, Young-Kook (Dep. of Electronic, Electrical, Control and Instrumentation Engineering, Hanyang Univ.)
Roh, Jeong-Jin (Dep. of Electronic, Electrical, Control and Instrumentation Engineering, Hanyang Univ.)
Publication Information
Journal of the Institute of Electronics Engineers of Korea SD / v.46, no.6, 2009 , pp. 16-24 More about this Journal
Abstract
In this paper, DC-DC buck converter with on-chip filter inductor and capacitor is presented. By operating at high switching frequency of 50MHz with stacked interleaved topology, we reduced inductor and capacitor sizes compared to previously published DC-DC buck converters. The proposed circuit is designed in a standard $0.5{\mu}m$ CMOS process, and chip area is $9mm^2$. This circuit operated at the input voltage of $3{\sim}5V$ range, the maximum load current of 250mA, and the maximum efficiency of 71%.
Keywords
Power management; buck converter; on-chip; ripple cancellation;
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