• 대한전자공학회논문지SD
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• 제47권11호
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• pp.30-36
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• 2010

최근의 메모리 반도체에 있어서, 수율과 품질을 유지하기 위하여 불량셀은 반드시 수리가 필요하다. 대부분의 워드단위 입출력을 갖는 system-on-chip (SoC)를 포함한 많은 메모리가 다중 블록으로 구성되어 있음에도 불구하고, 기존의 대부분의 자체내장수리연산회로의 연구들은 단일블록을 대상으로 하였다. 워드 단위 입출력 메모리의 특성상 다중메모리 광역대체수리구조를 갖는 경우가 많다. 본 논문에서는 이러한 메모리를 대상으로 기존에 최적 수리효율을 갖는 대표적인 자체내장 수리연산 회로인 CRESTA를 기본으로 하여, 보다 적은 면적으로 최적 수리효율을 낼 수 있는 알고리즘과 연산회로을 제안한다. 제안하는 자체내장수리 회로는 단위블록의 연산결과를 순차적으로 비교하여 워드단위 메모리의 제약조건을 만족시키는 최종 수리해를 구해내며, 기존의 회로보다 훨씬 빠른 시간 내에 최적의 수리 해를 구해 낼 수 있다.

• 대한임베디드공학회논문지
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• 제11권2호
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• pp.97-105
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• 2016

Microcontrollers (MCUs) for endpoint smart sensor devices of internet-of-thing (IoT) are being implemented as system-on-chip (SoC) with on-chip instruction flash memory, in which user firmware is embedded. MCUs directly fetch binary code-based instructions through bit-line sense amplifier (S/A) integrated with on-chip flash memory. The S/A compares bit cell current with reference current to identify which data are programmed. The S/A in reading '0' (erased) cell data consumes a large sink current, which is greater than off-current for '1' (programmed) cell data. The main motivation of our approach is to reduce the number of accesses of erased cells by binary code level transformation. This paper proposes a built-in write/read path architecture using binary code inversion method based on hot-spot region detection of instruction code access to reduce sensing current in S/A. From the profiling result of instruction access patterns, hot-spot region of an original compiled binary code is conditionally inverted with the proposed bit-inversion techniques. The de-inversion hardware only consumes small logic current instead of analog sink current in S/A and it is integrated with the conventional S/A to restore original binary instructions. The proposed techniques are applied to the fully-custom designed MCU with ARM Cortex-M0$^{TM}$ using 0.18um Magnachip Flash-embedded CMOS process and the benefits in terms of power consumption reduction are evaluated for Dhrystone$^{TM}$ benchmark. The profiling environment of instruction code executions is implemented by extending commercial ARM KEIL$^{TM}$ MDK (MCU Development Kit) with our custom-designed access analyzer.

• 전자공학회논문지A
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• 제31A권3호
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• pp.28-39
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• 1994

We experimented on memory multichip modules to increase the packing density of memory devices and to improve their electrical characteristics. A 128K$\times$8bit SRAM module was made of four 32K$\times$8bit SRAM memory chips. The memory multichip module was constructed on a low-cost double sided PCB(printed circuit boared) substrate. In the process of fabricating a multichip module. we focused on the improvement of its electrical characteristics. volume, and weight by employing bare memory chips. The characteristics of the bare chip module was compared with that of the module with four packaged chips. We conducted circuit routing with a PCAD program, and found the followings: the routed area for the module with bare memory chips reduced to a quarter of that area for module with packaged memory chips. 1/8 in volume, 1/5 in weight. Signal transmission delay times calculated by using transmission line model was reduced from 0.8 nsec to 0.4 nsec only on the module board, but the coupling coefficinet was not changed. Thus, we realized that the electrical characteristics of multichip packages on PCB board be improved greatly when using bare memory chips.

• 한국통신학회논문지
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• 제40권9호
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• pp.1754-1766
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• 2015

인터넷 라우터에서 행해지는 패킷분류는 5가지 패킷 헤더를 검사하여 선속도로 처리해야하기 때문에, 라우터가 수행하기 어려운 기능 중 하나이다. 본 논문에서는 리프-푸싱 된 영역분할 사분트라이 기반 비트맵 트라이 구조 (leaf-pushed AQT bitmap trie)를 제안한다. 제안하는 구조는 영역분할 사분트라이(Area-based Quad Trie, AQT)에 기초하되 불필요한 칩-외부메모리 접근을 줄이고자 리프-푸싱(leaf-pushing)기법을 적용하고, 멀티 비트 트라이인 비트맵을 적용하여 패킷분류 속도와 확장성을 모두 향상시킨 구조이다. 성능 평가를 위하여 ACL FW, IPC 룰셋을 각각 1k, 5k, 10k로 크기를 증가시키며 실험을 진행하였다. 그 결과, 제안하는 구조에서는 룰 셋의 종류나 크기와는 상관없이 패킷분류를 위하여 필요한 칩-외부메모리 접근 횟수가 1번 이내임을 확인할 수 있었다. 또한, 비트맵 트라이를 적용함으로 인해, 리프-푸싱기반 영역분할 사분트라이와 비교하여 약 50%의 칩-내부메모리 접근이 요구됨을 보았으며, 또한 칩-내부메모리 요구량의 변화폭이 룰 셋이 증가함에 따라 안정적으로 변화하여 제안하는 구조의 확장성을 확인할 수 있었다.

• 한국통신학회:학술대회논문집
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• 한국통신학회 1990년도 하계종합학술발표회 논문집
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• pp.539-542
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• 1990

• 한국통신학회논문지
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• 제21권11호
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• pp.2850-2861
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• 1996

This paper describes the design of AATM switch LIS of shared buffer type with linked-list architecture to control memory access. The proposed switch LSI consists of the buffer memory, controller and FIFO memory blocks and two special circuits to avoid the cell blocking. One of the special circuit is a new address control scheme with linked-list architecture which maintains the address of buffer memory serially ordered from write address to read address. All of the address is linked as chain is operated like a FIFO. The other is slip-flag register it will be hold the address chain when readaddress missed the reading of data. The circuits control the buffer memory efficiently and reduce the cell loss rate. As a result the designed chip operates at 33ns and occupied on 2.7*2.8mm$^{2}$ using 0.8.mu.m CMOS technology.

• 한국멀티미디어학회논문지
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• 제2권4호
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• pp.367-377
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• 1999

최근 들어 신속한 트랜잭션 처리를 요구하는 데이터베이스 응용이 확대되고 있다. 트랜잭션 처리 시스템에서 높은 성능을 달성하기 위한 한가지 방법으로 데이터베이스를 디스크가 아닌 주기억장치에 모두 상주시키는 것이다. 반도체 메모리의 집적도가 증가하고 가격이 하락함에 따라 모든 데이터베이스를 주기억장치에 상주시켜 트랜잭션 처리율을 높이기 위한 연구가 이루어지고 있다. 본 논문에서는 주기억장치 데이터베이스를 기반으로 한 고성능 트랜잭션 처리 시스템을 구현하기 위하여 새로운 병행수행 제어 기법과 회복 기법 그리고 저장 구조를 제안하며, 트랜잭션의 처리량과 응답속도로 평가되는 트랜잭션 처리 시스템 성능의 개선을 목적으로 한다.

• 전자공학회논문지C
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• 제34C권8호
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• pp.8-21
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• 1997

In this paper, we consider resistive shorts on gate-source, gate-drain, and drain-source as well as opens in MOS FETs included in typical memory cell of VLSI SRAM and analyze behavior of memory by using PSPICE simulation. Using conventional fault models and this behavioral analysis, we propose linear testing algorithm of complexity O(N) which can be applied to both functional testing and IDDQ (quiescent power supply current) testing simultaneously to improve functionality and reliability of memory. Finally, we implement BIST (built-in self tsst) circuit and BICS(built-in current sensor), which are embedded on memory chip, to carry out functional testing efficiently and to detect various defects at high-speed respectively.

• 한국정보과학회:학술대회논문집
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• 한국정보과학회 2008년도 한국컴퓨터종합학술대회논문집 Vol.35 No.1 (A)
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• pp.335-336
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• 2008

• 음성과학
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• 제14권4호
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• pp.157-167
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• 2007

In this paper, we implemented a single-chip speech recognizer using the TMS320C2000 DSPs. For this implementation, we had developed very small-sized speaker-dependent recognition engine based on dynamic time warping, which is especially suited for embedded systems where the system resources are severely limited. We carried out some optimizations including speed optimization by programming time-critical functions in assembly language, and code size optimization and effective memory allocation. For the TMS320F2801 DSP which has 12Kbyte SRAM and 32Kbyte flash ROM, the recognizer developed can recognize 10 commands. For the TMS320F2808 DSP which has 36Kbyte SRAM and 128Kbyte flash ROM, it has additional capability of outputting the speech sound corresponding to the recognition result. The speech sounds for response, which are captured when the user trains commands, are encoded using ADPCM and saved on flash ROM. The single-chip recognizer needs few parts except for a DSP itself and an OP amp for amplifying microphone output and anti-aliasing. Therefore, this recognizer may play a similar role to dedicated speech recognition chips.