• Korean Journal of Fisheries and Aquatic Sciences
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• v.45 no.6
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• pp.545-552
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• 2012

This study developed a natural seasoning (NS) and characterized its food components. Hydrolysate from Alaska Pollock Theragra chalcogramma heads and sea tangle Laminaria japonica byproduct were obtained by incubating them with Neutrase for 4 h. NS was prepared by mixing sorbitol 2%, salt 2%, ginger powder 0.04%, garlic powder 0.2%, onion powder 0.2% and inosine monophosphate (IMP) 0.1% based on concentrated hydrolysates from Alaska pollock head and sea tangle byproduct before vaccum filtering. The proximate composition of NS was 82.7% moisture, 9.0% crude protein, and 5.1% ash. It had a higher crude protein content than commercial anchovy sauce (CS), it was lower in moisture and ash. The 1,1-diphenyl-2-picrylhydrazyl (DPPH) radical scavenging activity and angiotensin-I converting enzyme (ACE) inhibiting activity of NS were 90.1% and 88.9%, respectively, which were superior to those of CS. The free amino acid content and total taste value of NS were 1,626.0 mg/100 mL and 165.86, respectively, which were higher than those of CS. According to the results of taste value, the major free amino acids were glutamic acid and aspartic acid. In the sensory evaluation, the color and taste of NS were superior to those of CS. No difference in fish odor between NS and CS was found.

• Journal of the Korean Chemical Society
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• v.57 no.1
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• pp.109-114
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• 2013

The effects of aluminum nanoparticles (AlNs) on the thermal decomposition of ammonia perchlorate (AP) were investigated by DSC, TG-DSC and DSC-TG-MS-FTIR. Addition of AlNs resulted in an increase in the temperature of the first exothermic peak of AP and a decrease in the second. The processing of non-isothermal data at various heating rates with and without AlNs was performed using Netzsch Thermokinetics. The dependence of the activation energy calculated by Friedman's isoconversional method on the conversion degree indicated the decomposition process can be divided into three steps. They were C1/D1/D1 for neat AP, determined by Multivariate Non-linear Regression, and changed to C1/D1/F2 after addition of AlNs into AP. The isothermal curves showed that the thermal stability of AP in the low temperature stage was improved in the presence of AlNs.

• Journal of Microbiology and Biotechnology
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• v.16 no.10
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• pp.1634-1639
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• 2006

Hepatitis C virus (HCV)-encoded nonstructural protein 5B (NS5B) possesses RNA-dependent RNA polymerase activity, which is considered essential for viral proliferation. Thus, HCV NS5B is a good therapeutic target protein for the development of anti-HCV agents. In this study, we isolated two different kinds of nuclease-resistant RNA aptamers with 2'-fluoro pyrimidines against the HCV NS5B from a combinatorial RNA library with 40 nucleotide random sequences, using SELEX technology. The isolated RNA aptamers were observed to specifically and avidly bind the HCV NS5B with an apparent $K_d$ of 5 nM and 18 nM, respectively, in contrast with the original RNA library that hardly bound the target protein. Moreover, these aptamers could partially inhibit RNA synthesis of the HCV subgenomic replicon when transfected into Huh-7 hepatoma cell lines. These results suggest that the RNA aptamers selected in vitro could be useful not only as therapeutic agents of HCV infection but also as a powerful tool for the study of the HCV RNA-dependent RNA polymerase mechanism.

• Journal of The Korea Institute of Healthcare Architecture
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• v.21 no.2
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• pp.17-24
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• 2015

Purpose: This study examines distance from nurse station to bed according to composition of single bedroom. Methods: This study has two groups of target sample ward planes. The first group has diverse patients bedroom. The other group is 36 single bedrooms and 2 3-bedrooms. The guideline of distance measurement was instituted for consistency. This study has 3 main concepts of the guideline. 1) The distance is shortcut from NS to bed. 2) The traffic line is center line between walls and center of door. 3) The start point is center of NS and the end point is bed. Results: The result of this study can be summarized into two points. The first one is that single bedroom has good privacy and longer distance from NS to bed. The second one is that weak point of single bedroom was asked ward operating system and architectural planning like as patients room, bed per unit, location of NS and plan type. Implications: Consideration Should be taken into account for the effective bedroom composition and allocation in ward. This Stuy hopefully serve as a stepping stone for the standard design of space program in ward planning.

• The Journal of the Korea institute of electronic communication sciences
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• v.7 no.4
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• pp.741-746
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• 2012

Transmission control protocol(TCP) widely used as a transport protocol in the Internet includes a loss recovery function that detects and recovers packet losses by retransmissions. The loss recovery function consists of the two algorithms; fast retransmit and fast recovery. There have been researches to avoid nonnecessary retransmission timeouts (RTOs), which leads to selective acknowledgement (SACK) option and limited transmit scheme that are standardized by IETF (Internet Engineering Task Force). Recently, a method that covers the case in which a retransmitted packet is lost again has been propsed. The method, however, is not proved in terms of the additive increase multiplicative decrease (AIMD) principle of TCP congestion control. In this paper, therefore, we analyzed the method in terms of the principle by ns-simulations.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.38 no.2
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• pp.38-49
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• 2001

This paper presents a new voltage down converter(VDC) using charge and discharge current adjustment circuitry that provides high frequency application. This VDC consist of a common driving circuit and compensation circuits: 2 sensors and each driving transistors for controlling gate current of driving transistor. These sensors are operated as adaptive biasing method with high speed and low power consumption. This circuit is designed with a $0.62{\mu}m$ N well CMOS technology. In H-spice simulation results, internal voltage is bounded ( IV, +0.6V) in proposed circuitry when load current rapidly increases and decreases during Gns between 0 and $200m{\Lambda}$. And the recovery time of internal voltage is about 7ns and 10ns when load current increases and decreases respectively. That is fast better than common driving circuit. Total power consumption is about 1.2mW.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2007.10a
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• pp.187-191
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• 2007

This paper describes a 3.3V 10 bit CMOS digital-to-analog converter with a divided architecture of a 7 MSB and a 3 LSB, which uses an optimal Thermal-to-Binary Decoding method with monotonicity, glitch energy. The output stage utilizes here implements a return-to-zero circuit to obtain the dynamic performance. Most of D/A converters in decoding circuit is complicated, occupies a large chip area. For these problems, this paper describes a D/A converter using an optimal Thermal-to-Binary Decoding method. the designed D/A converter using the CMOS n-well $0.35{\mu}m$ process0. The experimental data shows that the rise/fall time, settling time, and INL/DNL are 1.90ns/2.0ns, 12.79ns, and a less than ${\pm}2.5/{\pm}0.7$ LSB, respectively. The power dissipation of the D/A converter with a single power supply of 3.3V is about 250mW.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.12 no.4
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• pp.691-698
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• 2008

This paper describes a 3.3V 10 bit CMOS digital-to-analog converter with a divided architecture of a 7 MSB and a 3 LSB, which uses an optimal Thermal-to-Binary Decoding method with monotonicity, glitch energy. The output stage utilizes here implements a return-to-zero circuit to obtain the dynamic performance. Most of D/A converters in decoding circuit is complicated, occupies a large chip area. For these problems, this paper describes a D/A converter using an optimal Thermal-to-Binary Decoding method. the designed D/A converter using the CMOS n-well $0.35{\mu}m$ process0. The experimental data shows that the rise/fall time, settling time, and INL/DNL are 1.90ns/2.0ns, 12.79ns, and a less than ${\pm}2.5/{\pm}0.7\;LSB$, respectively. The power dissipation of the D/A converter with a single power supply of 3.3V is about 250mW.

• The Transactions of the Korean Institute of Power Electronics
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• v.10 no.6
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• pp.560-568
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• 2005

The proposed Multi-level PDP sustain Driver is composed of the semiconductor devices with low voltage rating compared to those used in the prior circuit proposed by L. Wether, and it has two resonant periods during the charging (rising period) and discharging (falling period) the PDP in the sustaining voltage waveforms. In accordance with the change of timing phase$(T_{r1},\;T_{i1},\;T_{r2})$, the performance characteristics of a commercial PDP module has been carried out and compared the characteristic with the 42V6, made of LG Electronics co., Experimental results show that the performance characteristics of PDP module are greatly influenced by the variation of $T_{i1}\;and\;T_{r2}$. The variation of $T_{r1}$ do not influence much on the performances of PDP. With the conditions that $T_{r1}=60ns,\;T_{i1}=120ns,\;and\;T_{r2}=350ns$, we could get the performances listed as the luminance is increased $14.6\%$, the power consumptions is decreased $5.9\%$, the panel efficiency is increased $24.2\%$, module efficiency is increased $21.2\%$, compared to those shown in the commercial PDP module (42V6). Therefore, the proposed multi-level PDP sustain driver expected to be suitable to actual PDP module application.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.28A no.11
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• pp.915-922
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• 1991

This research paper presents an ALU unit using 1.0$\mu$m CMOS technology capable of doing IEEE standard single and double precision floating poing calculation within 32ns (2 clock) at 60 MHz clock speed. This 32ns speed was achieved by using 9ns 1's complement arithmetic 54 bit carry select adder instead of previous 2's complement adders. On the first cycle, this adder is used for addition or subtraction and the second cycle uses this adder for rounding. This reduces the number of required adders from two to one. Speed improvement is 2 to 5 times compared with previous 40MHz design. Design goal was 60MHz, however, this unit is functioning at 80 MHz at room temperature.