• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.06a
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• pp.133-133
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• 2009

It is desirable to choose a high-k material having a large band offset with the tunneling oxide and a deep trapping level for use as the charge trapping layer to achieve high PIE (Programming/erasing) speeds and good reliability, respectively. In this paper, charge trapping and tunneling characteristics of high-k hafnium oxide ($HfO_2$) layer with various thicknesses were investigated for applications of tunnel barrier engineered nonvolatile memory. A critical thickness of $HfO_2$ layer for suppressing the charge trapping and enhancing the tunneling sensitivity of tunnel barrier were developed. Also, the charge trap centroid and charge trap density were extracted by constant current stress (CCS) method. As a result, the optimization of $HfO_2$ thickness considerably improved the performances of non-volatile memory(NVM).

• Journal of Microbiology and Biotechnology
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• v.17 no.10
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• pp.1682-1687
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• 2007

The differences in the nonvolatile metabolites of pine-mushrooms (Tricholoma matsutake Sing.) according to different parts and heating times were analyzed by applying principal component analysis (PCA) to $^1H$ nuclear magnetic resonance (NMR) spectroscopy data. The $^1H$ NMR spectra and PCA enabled the differences of nonvolatile metabolites among mushroom samples to be clearly observed. The two parts of mushrooms could be easily discriminated based on PC 1, and could be separated according to different heattreated times based on PC 3. The major peaks in the $^1H$ NMR spectra that contributed to differences among mushroom samples were assigned to trehalose, succinic acid, choline, leucine/isoleucine, and alanine. The content of trehalose was higher in the pileus than in the stipe of all mushroom samples, whereas succinic acid, choline, and leucine/isoleucine were the main components in the stipe. Heating resulted in significant losses of alanine and leucine/isoleucine, whereas succinic acid, choline, and trehalose were the most abundant components in mushrooms heat-treated for 3 min and 5 min, respectively.

• Proceedings of the Materials Research Society of Korea Conference
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• 2011.05a
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• pp.28.2-28.2
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• 2011

Resistance random access memory (ReRAM) is a promising candidate for next-generation nonvolatile memory because of its advantageous qualities such as simple structure, superior scalability, fast switching speed, low-power operation, and nondestructive readout. We investigated the resistive switching behavior of tantalum oxide that has been widely used in dynamic random access memories (DRAM) in the present semiconductor industry. As a result, it possesses full compatibility with the entrenched complementary metal-oxide-semiconductor processes. According to previous studies, TiN is a good oxygen reservoir. The TiN top electrode possesses the specific properties to control and modulate oxygen ion reproductively, which results in excellent resistive switching characteristics. This study presents fully room temperature fabricated the TiN/$TaO_x$/Pt devices and their electrical properties for nonvolatile memory application. In addition, we investigated the TiN electrode dependence of the electrical properties in $TaO_x$ memory devices. The devices exhibited a low operation voltage of 0.6 V as well as good endurance up to $10^5$ cycles. Moreover, the benefits of high devise yield multilevel storage possibility make them promising in the next generation nonvolatile memory applications.

• JSTS:Journal of Semiconductor Technology and Science
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• v.8 no.1
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• pp.27-31
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• 2008

We have studied nonvolatile memory properties of MOSFETs with double-stacked Si nanoclusters in the oxide-gate stacks. We formed Si nanoclusters of a uniform size distribution on a 5 nm-thick tunneling oxide layer, followed by a 10 nm-thick intermediate oxide and a second layer of Si nanoclusters by using LPCVD system. We then investigated the memory characteristics of the MOSFET and observed that the charge retention time of a double-stacked Si nanocluster MOSFET was longer than that of a single-layer device. We also found that the double-stacked Si nanocluster MOSFET is suitable for use as a dual-bit memory.

• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.395-396
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• 2008

There is difficulty in predicting the program efficiency of NOR type nonvolatile memory device adopting channel hot electron injection (CHEI) as program operation mechanism accurately since MOSFET on SOI has floating body. In this study, the dependence of program efficiency for SOI nonvolatile memory device of 200 nm channel length on SOI depletion conditions, partial depletion and full depletion, was quantitatively investigated with the aid of numerical device simulation [1].

• IEMEK Journal of Embedded Systems and Applications
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• v.11 no.2
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• pp.87-95
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• 2016

Nonvolatile memory (NVM) is being considered as an alternative of traditional memory devices such as SRAM and DRAM, which suffer from various limitations due to the technology scaling of modern integrated circuits. Although NVMs have advantages including nonvolatility, low leakage current, and high density, their inferior write performance in terms of energy and endurance becomes a major challenge to the successful design of NVM-based memory systems. In order to overcome the aforementioned drawback of the NVM, extensive research is required to develop energy- and endurance-aware optimization techniques for NVM-based memory systems. However, researchers have experienced difficulty in finding a suitable simulation tool to prototype and evaluate new NVM optimization schemes because existing simulation tools do not consider the feature of NVM devices. In this article, we introduce a NVM-based cache simulator to support rapid prototyping and evaluation of NVM-based caches, as well as energy- and endurance-aware NVM cache optimization schemes. We demonstrate that the proposed NVM cache simulator can easily prototype PRAM cache and PRAM+STT-RAM hybrid cache as well as evaluate various write traffic reduction schemes and wear leveling schemes.

• Journal of the Korean Society of Tobacco Science
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• v.6 no.2
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• pp.169-178
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• 1984

This study was conducted to investigate the influence of the topping time and height on the nonvolatile organic and higher fatty acid contents and the correlation among acid contents of tobacco plants. Within the topping time, the flowering (normal) stage of topping was the lowest in total analyzed acid (TAA), total nonvolatile organic acid (TNOA) and magic acid contents of NC2326, however, the highest in those of Burley 21 on 30 days after budding. Total higher fatty acid (THFA) and linoleic acid contents tended to be low with normal stage of topping. The lower the topping height, the lower the TAA, THFA and linoleic acid contents in middle and upper leaves (or NC2326 and Burley 21 were observed. On the other hand, the lower the topping height, the lower the TNOA and malic acid contents in middle and upper leaves for Burley 21 and upper leaves for NC2326 were found. There was a significant positive correlation between magic acid and TNOA contents. Similarly, TAA content showed a significant positive correlation with TNOA, oxalic acid and citric acid contents. But there was a negative correlation between malic acid and THFA contents. There were highly positive correlations among oleic acid, linoleic acid and THFA contents, respectively.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.16 no.1
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• pp.5-10
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• 2003

In this study, a new programming method to minimize the generation of Si-SiO$_2$interface traps of SONOS nonvolatile memory device as a function of number of porgram/erase cycles was proposed. In the proposed programming method, power supply voltage is applied to the gate. forward biased program voltage is applied to the source and the drain, while the substrate is left open, so that the program is achieved by Modified Fowler-Nordheim(MFN) tunneling of electron through the tunnel oxide over source and drain region. For the channel erase, erase voltage is applied to the gate, power supply voltage is applied to the substrate, and the source and dram are left open. Also, the asymmetric mode in which the program voltage is higher than the erase voltage, is more efficient than symmetric mode in order to minimize the degradation characteristics or SONOS devices because electrical stress applied to the Si-SiO$_2$interface is reduced due to short program time.

• Transactions on Electrical and Electronic Materials
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• v.5 no.6
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• pp.227-232
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• 2004

We investigated a nonvolatile nanomemory element based on boron nitride nanopeapods using molecular dynamics simulations. The studied system was composed of two boron-nitride nanotubes filled Cu electrodes and fully ionized endo-fullerenes. The two boron-nitride nanotubes were placed face to face and the endo-fullerenes came and went between the two boron-nitride nanotubes under alternatively applied force fields. Since the endo-fullerenes encapsulated in the boron-nitride nanotubes hardly escape from the boron-nitride nanotubes, the studied system can be considered to be a nonvolatile memory device. The minimum potential energies of the memory element were found near the fullerenes attached copper electrodes and the activation energy barrier was $3{\cdot}579 eV$. Several switching processes were investigated for external force fields using molecular dynamics simulations. The bit flips were achieved from the external force field of above $3.579 eV/{\AA}$.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.22 no.1
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• pp.17-21
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• 2009

The electrical characteristics of band-gap engineered tunneling barriers consisting of thin $SiO_2$ and $Si_3N_4$ dielectric layers were investigated for nonvolatile memory device applications. The band structure of band-gap engineered tunneling barriers was studied and the effectiveness of these tunneling barriers was compared with the conventional tunneling $SiO_2$ barrier. The band-gap engineered tunneling barriers composed of thin $SiO_2$ and $Si_3N_4$ layers showed a lower operation voltage, faster speed and longer retention time than the conventional $SiO_2$ tunnel barrier. The thickness of each $SiO_2$ and $Si_3N_4$ layer was optimized to improve the performance of non-volatile memory.