• E2M - 전기 전자와 첨단 소재
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• 제9권5호
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• pp.476-482
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• 1996

The multi-dielectric layer SiO$_{2}$/Si$_{3}$N$_{4}$/SiO$_{2}$(ONO) is used to improve electrical capacitance and to scale down the memory device. In this paper, improvement of the capacitance by reducing the bottom oxide thickness in the nitride deposition with load lock(L/L) vacuum system is studied. Bottom oxide thickness under the nitride layer is measured by ellipsometer both in L/L and non-L/L systems. Both results are in the range of 3-10.angs. and 10-15.angs., respectively, independent of the nitride and top oxide thickness. Effective thickness and cell capacitance for SONOS capacitor are in the range of 50-52.angs. and 35-37fF respectively in the case of nitride 70.angs. in L/L vacuum system. Compared with non-L/L system, the bottom oxide thickness in the case of L/L system decreases while cell capacitance increases about 4 fF. The results obtained in this study are also applicable to ONO scaling in the thin bottom oxide region of memory stacked capacitor.

• 한국정보통신학회논문지
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• 제7권2호
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• pp.269-275
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• 2003

저전압 프로그래밍이 가능한 플래시메모리를 실현하기 위하여 0.35$\mu\textrm{m}$ CMOS 공정 기술을 이용하여 터널링산화막, 질화막 그리고 블로킹산화막의 두께가 각각 2.4nm, 4.0nm, 2.5nm인 SONOS 트랜지스터를 제작하였으며, SONOS 메모리 셀의 면적은 1.32$\mu$$m^2$이었다. 질화막의 두께를 스케일링한 결과, 10V의 동작 전압에서 소거상태로부터 프로그램상태로, 반대로 프로그램상태에서 소거상태로 스위칭 하는데 50ms의 시간이 필요하였으며, 최대 메모리윈도우는 1.76V이었다. 그리고 질화막의 두께를 스케일링함에도 불구하고 10년 후에도 0.5V의 메모리 윈도우를 유지하였으며, 105회 이상의 프로그램/소거 반복동작이 가능함을 확인하였다. 마지막으로 부유게이트 소자에서 심각하게 발생하고있는 과도소거현상이 SONOS 소자에서는 나타나지 않았다.

• 한국세라믹학회지
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• 제45권9호
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• pp.507-511
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• 2008

A "C-sphere" specimen geometry was used to determine the failure strength distributions of a commercially-available bearing-grade silicon nitride ($Si_3N_4$) with ball diameters of 12.7 and 25.4 mm. Strengths for both diameters were determined using the combination of failure load, C-sphere geometry, and finite element analysis and fitted using two-parameter Weibull distributions. Effective areas of both diameters were estimated as a function of Weibull modulus and used to explore whether the strength distributions predictably scaled between each size. They did not. That statistical observation suggested that the same flaw type did not limit the strength of both ball diameters indicating a lack of material homogeneity between the two sizes. Optical fractography confirmed that. It showed there were two distinct strength-limiting flaw types common to both ball diameters, that one flaw type was always associated with lower strength specimens, and that a significantly higher fraction of the 25.4-mm-diameter C-sphere specimens failed from it. Predictable strength-size-scaling would therefore not result as a consequence of this because these flaw types were not homogenously distributed and sampled in both C-sphere geometries.

• The Journal of Advanced Prosthodontics
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• 제10권3호
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• pp.197-204
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• 2018

PURPOSE. To determine the extent of treatment traces, the roughness depth, and the quantity of titanium nitride (TiN) removed from the surface of CAD/CAM abutments after treatment with various instruments. MATERIALS AND METHODS. Twelve TiN coated CAD/CAM abutments were investigated for an in vitro study. In the test group (9), each abutment surface was subjected twice (150 g vs. 200 g pressure) to standardized treatment in a simulated prophylaxis measure with the following instruments: acrylic scaler, titanium curette, and ultrasonic scaler with steel tip. Three abutments were used as control group. Average surface roughness (Sa) and developed interfacial area ratio (Sdr) of treated and untreated surfaces were measured with a profilometer. The extent of treatment traces were analyzed by scanning electron microscopy. RESULTS. Manipulation with ultrasonic scalers resulted in a significant increase of average surface roughness (Sa, P<.05) and developed interfacial area ratio (Sdr, P<.018). Variable contact pressure did not yield any statistically significant difference on Sa-values for all instruments (P=.8). Ultrasonic treatment resulted in pronounced surface traces and partially detachment of the TiN coating. While titanium curettes caused predominantly moderate treatment traces, no traces or detectable substance removal has been determined after manipulation with acrylic curettes. CONCLUSION. Inappropriate instruments during regular plaque control may have an adverse effect on the integrity of the TiN coating of CAD/CAM abutments. To prevent defects and an increased surface roughness at the transmucosal zone of TiN abutments, only acrylic scaling instruments can be recommended for regular maintenance care.

• 한국전기전자재료학회논문지
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• 제11권1호
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• pp.33-40
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• 1998

The composite SiO$_2$/Si$_3$N$_4$/SiO$_2$(ONO) film formed by oxidation on nitride film has been widely studied as DRAM stacked capacitor multi-dielectric films. Load lock(L/L) LPCVD system by HF cleaning is used to improve electrical capacitance and to scale down of effective thickness for memory device, but is brings a new problem. Nitride film deposited using HF cleaning shows selective deposition on poly silicon and oxide regions of capacitor. This problem is avoidable by carpeting chemical oxide using $H_2O$$_2$cleaning before nitride deposition. In this paper, we study the limit of nitride thickness for abnormal oxidation and the initial deposition time for nitride deposition dependent on underlayer materials. We proposed an advanced fabrication process for stacked capacitor in order to avoid selective deposition problem and show the usefulness of nitride deposition using L/L LPCVD system by $H_2O$$_2$cleaning. The natural oxide thickness on polysilicon monitor after HF and $H_2O$$_2$cleaning are measured 3~4$\AA$, respectively. Two substrate materials have the different initial nitride deposition times. The initial deposition time for polysilicon is nearly zero, but initial deposition time for oxide is about 60seconds. However the deposition rate is constant after initial deposition time. The limit of nitride thickness for abnormal oxidation under the HF and $H_2O$$_2$cleaning method are 60$\AA$, 48$\AA$, respectively. The results obtained in this study are useful for developing ultra thin nitride fabrication of ONO scaling and for avoiding abnormal oxidation in stacked capacitor application.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2014년도 제46회 동계 정기학술대회 초록집
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• pp.211.1-211.1
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• 2014

Recently, the scaling of conventional planar NAND flash devices is facing its limits by decreasing numbers of electron stored in the floating gate and increasing difficulties in patterning. Three-dimensional vertical NAND devices have been proposed to overcome these issues. Atomic layer deposition (ALD) is the most promising method to deposit charge trap layer of vertical NAND devices, SiN, with excellent quality due to not only its self-limiting growth characteristics but also low process temperature. ALD of silicon nitride were studied using NH3 and silicon chloride precursors, such as SiCl4[1], SiH2Cl2[2], Si2Cl6[3], and Si3Cl8. However, the reaction mechanism of ALD silicon nitride process was rarely reported. In the present study, we used density functional theory (DFT) method to calculate the reaction of silicon chloride precursors with a silicon nitride surface. DFT is a quantum mechanical modeling method to investigate the electronic structure of many-body systems, in particular atoms, molecules, and the condensed phases. The bond dissociation energy of each precursor was calculated and compared with each other. The different reactivities of silicon chlorides precursors were discussed using the calculated results.

• E2M - 전기 전자와 첨단 소재
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• 제8권6호
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• pp.727-736
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• 1995

This paper examines the characteristics and physical properties of the scaled MONOS nonvolatile memory device for low programming voltage EEPROM. The capacitor-type MONOS memory devices with the nitride thicknesses ranging from 41.angs. to 600.angs. have been fabricated. As a result, the 5V-programmable MONOS device has been obtained with a 20ms programming time by scaling the nitride thickness to 57.angs. with a tunneling oxide thickness of 19.angs. and a blocking oxide thickness of 20.angs.. Measurement results of the quasi-static C-V curves indicate, after 10$\^$6/ write/erase cycles, that the devices are degraded due to the increase of the silicon-tunneling oxide interface traps. The 10-year retention is impossible for the device with a nitride less than 129.angs.. However, the MONOS memory device with 10-year retentivity has been obtained by increasing the blocking oxide thickness to 47.angs.. Also, the memory traps such as the nitride bulk trap and the blocking oxide-nitride interface trap have been investigated by measuring the maximum flatband voltage shift and analyzing through the best fitting method.

• E2M - 전기 전자와 첨단 소재
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• 제7권2호
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• pp.123-129
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• 1994

SONOS EEPROM chips, containing several SONOSFET nonvolatile memories of various channel size, have been fabricated on the basis of the existing n-well CMOS processing technology for 1 Mbit DRAM ($1.2\mu\textrm{m}$.m design rule). All the SONOSFET memories have the triple insulated-gate consisting of 30.angs. tunneling oxide, 205.angs. nitride and 65.angs. blocking oxide. The miniaturization of the devices for the higher density EEPROM and their characteristics alterations accompanied with the scaling-down have been investigated. The stabler operating characteristics were attained by increasing the ratio of the channel width to length. Also, the transfer, switching, retention and degradation characteristics of the most favorable performance devices were presented and discussed.

• 전자통신동향분석
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• 제34권5호
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• pp.71-80
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• 2019

Gallium nitride (GaN) can be used in high-voltage, high-power-density/-power, and high-speed devices owing to its characteristics of wide bandgap, high carrier concentration, and high electron mobility/saturation velocity. In this study, we investigate the technology trends for X-/Ku-band GaN RF power devices and MMIC power amplifiers, focusing on gate-length scaling, channel structure, and power density for GaN RF power devices and output power level and output power density for GaN MMIC power amplifiers. Additionally, we review the technology trends in gallium arsenide (GaAs) RF power devices and MMIC power amplifiers and analyze the technology trends in RF power devices and MMIC power amplifiers based on both GaAs and GaN. Furthermore, we discuss the current direction of national research by examining the national and international technology trends with respect to X-/Ku-band power devices and MMIC power amplifiers.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2008년도 추계학술대회 논문집 Vol.21
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• pp.122-122
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• 2008

Recently, Metal/Alumina/Silicon-Nitride/Silicon-Oxide/Silicon (MANOS) structures are one of the most attractive candidates to realize vertical scaling of high-density NAND flash memory [1]. However, as ANO layers are miniaturized, negative and positive bias temperature instability (NBTI/PBTI), such as the flat band voltage shift, ${\Delta}V_{FB}$, the interfacial trap density increase, ${\Delta}D_{it}$, the gate leakage current, ${\Delta}I_G$. and the retention characteristics, in MONOS capacitors, becomes an important issue in terms of reliability. It is well known that tunnel oxide degradation is a result of the oxide and interfacial traps generation during FN (Fowler-Nordheim) stress [2]. Because the bias temperature stress causes an increase of both interfacial-traps and fixed oxide charge could be a factor, witch can degrade device reliability during the program and erase operation. However, few studies on NBTI/PBTI have been conducted on improving the reliability of MONOS devices. In this work, we investigate the effect of post-annealing gas on bias temperature instability (BTI), such as the flat band voltage shift, ${\Delta}V_{FB}$, the interfacial trap density shift, ${\Delta}I_G$ retention characteristics, and the gate leakage current characteristics of MANOS capacitors. MANOS samples annealed at $950^{\circ}C$ for 30 s by a rapid thermal process were treated via additional annealing in a furnace, using annealing gases $N_2$ and $N_2-H_2$ (2 % hydrogen and 98 % nitrogen mixture gases) at $450^{\circ}C$ for 30 min. MANOS samples annealed in $N_2-H_2$ ambient had the lowest flat band voltage shift, ${\Delta}V_{FB}$ = 1.09/0.63 V at the program/erase state, and the good retention characteristics, 123/84 mV/decade at the program/erase state more than the sample annealed at $N_2$ ambient.